Circuits and methods for implementing sub-integer-n frequency dividers using phase rotators

A PLL (phase-locked loop) frequency synthesizer, comprising:

• a phase detector;
• a low pass filter coupled to the output of the phase detector;
• a VCO (voltage controlled oscillator) coupled to the output of to low-pass filter;
• a fractional frequency divider circuit connected in a feedback loop between an output of the VCO and an input to the phase detector, wherein the fractional frequency divider circuit comprises:
• a prescaler circuit that divides a frequency of an input signal by a factor of A and outputs a plurality of phase-shifted signals each having a frequency of 1/A, the phase-shifted signals comprising differential I (in-phase) and Q (quadrature-phase) phase signals;
• a phase rotator circuit that can phase interpolate between the plurality of phase-shifted signals output from the prescaler circuit to generate a plurality of phase-shift states having a minimum phase-shift resolution of Δφ;
• a phase rotator controller that generates control signals to control the operation of the phase rotator circuit, wherein the phase rotator circuit, rotatably outputs one or more of the plurality of phase-shift states in accordance with an angular direction of rotation and a phase-shift output resolution, ±k Δφ, as specified by the control signals;
• a postscaler circuit that divides a frequency of an output signal of the phase rotator circuit by a factor of B, and which outputs a clock signal which controls the phase rotator controller and which defines a control cycle for the phase rotator circuit;
• wherein the fractional frequency divider circuit generates an arbitrary sub-integer-N divisor N(k)=(AB+Ak Δφ/2π), wherein at least k is a programmable parameter, wherein AB denotes an integer portion of the divisor, wherein
• A
• 
• 
• Δ
• 
• 
• φ
• 2
• 
• π
• denotes a minimum fractional portion of the divisor, and wherein A and B can be integer values ≧1.

A fractional frequency divider circuit, comprising:

• a prescaler circuit that divides a frequency of an input signal by a factor of A and outputs a plurality of phase-shifted signals each having a frequency of 1/A, the phase-shifted signals comprising differential I (in-phase) and Q (quadrature-phase) phase signals;
• a phase rotator circuit that can phase interpolate between the plurality of phase-shifted signals output from the prescaler circuit to generate a plurality of phase shift states having a minimum phase-shift resolution of Δφ;
• a modulus controller that generates control signals to control the operation of the phase rotator circuit, wherein the phase rotator circuit rotatably outputs one or more of the plurality of phase-shift states in accordance with an angular direction of rotation and a phase-shift output resolution as specified by the control signals, wherein the modulus controller comprises a phase rotator control circuit and a program-swallowed framework comprising a P counter and an S counter;
• a postscaler circuit that divides a frequency of an output signal of the phase rotator by a factor of B, and which outputs a clock signal which controls the modulus controller and defines a control cycle for the phase rotator circuit;
• wherein the fractional frequency divider circuit generates an arbitrary sub-integer-N divisor,
• N
• TOT
• 
• (
• k
• 1
• ,
• k
• 2
• )
• =
• ABP
• +
• A
• 
• Δφ
• 2
• 
• π
• 
• [
• Pk
• 2
• +
• S
• 
• (
• k
• 1
• -
• k
• 2
• )
• ]
• ,
• wherein at least k2 and k1 and S are programmable parameters, wherein ABP denotes an integer portion of the divisor and where
• A
• 
• 
• Δ
• 
• 
• φ
• 2
• 
• π
• denotes a minimum fractional portion of the divisor, and wherein A, B and P can be integer values ≧1, and wherein S can be an integer value ≧0 and ≦P.

A PLL (phase-locked loop) frequency synthesizer, comprising:

• a phase detector;
• a low pass filter coupled to the output of the phase detector;
• a VCO (voltage controlled oscillator) coupled to the output of the low pass filter;
• a fractional frequency divider circuit connected in a feedback loop between an output of the VCO and an input to the phase-frequency detector, wherein the fractional frequency divider circuit comprises:
• a prescaler circuit that divides a frequency of an input signal by a factor of A and outputs a plurality of phase-shifted signals each having a frequency 1/A, the phase-shifted signals comprising differential I (in-phase) and Q (quadrature-phase) phase signals;
• a phase rotator circuit that can phase interpolate between the plurality of phase-shifted signals output from the prescaler circuit to generate a plurality of phase-shift states having a minimum phase-shift resolution of Δφ;
• a modulus controller that generates control signals to control the operation of the phase rotator circuit, wherein the phase rotator circuit rotatably outputs one or more of the plurality of phase-shift states in accordance with an angular direction of rotation and a phase-shift output resolution as specified by the control signals, wherein the modulus controller comprises a phase rotator control circuit and a program-swallowed framework comprising a P counter and an S counter;
• a postscaler circuit that divides a frequency of an output signal of the phase rotator by a factor of B, and which outputs a clock signal which controls the modulus controller and defines a control cycle for the phase rotator circuit;
• wherein the fractional frequency divider circuit generates an arbitrary sub-integer-N divisor,
• N
• TOT
• 
• (
• k
• 1
• ,
• k
• 2
• )
• =
• ABP
• +
• A
• 
• Δφ
• 2
• 
• π
• 
• [
• Pk
• 2
• +
• S
• 
• (
• k
• 1
• -
• k
• 2
• )
• ]
• ,
• wherein at least k2 and k1 and S are programmable parameters, wherein ABP denotes an integer portion of the divisor and where
• A
• 
• 
• Δ
• 
• 
• φ
• 2
• 
• π
• denotes a minimum fractional portion of the divisor, and wherein A, B and P can be integer values ≧1, and wherein S can be an integer value ≧0 and ≦P.

A method for performing sub-integer frequency division of a frequency signal, comprising:

• dividing a frequency of an input signal by a factor of A
• phase interpolating between a plurality of phase-shifted signals each having, a frequency of 1/A of the input signal to generate a plurality of phase-shift states having a minimum phase-shift resolution of Δφ;
• rotatably outputting a phase state signal corresponding to one or more of the plurality of phase-shift states, based on control signals that specify an angular direction of rotation and a phase-shift output resolution;
• dividing a frequency of an output phase state signal by a factor of B so as to achieve a sub-integer-N divisor N(k)=(AB+Ak Δφ/2π), wherein at least k is a programmable parameter, wherein AB denotes an integer portion of the divisor and where
• A
• 
• 
• Δ
• 
• 
• φ
• 2
• 
• π
• denotes a minimum fractional portion of the divisor, and wherein A and B can be integer values ≧1.