US 2008/0164913 A1 · Peak-hold circuit and signal strength indicator using the peak-hold circuit

Abstract

A peak-hold circuit includes a differential amplifier having first and second transistors as a differential pair, the first transistor receiving an input signal at its gate, a third transistor connected between a first power supply and an output node connecting a gate of the second transistor, connectivity of the third transistor being controlled by the output of the differential amplifier, a capacitor for holding a peak voltage, connected between the output node and a second power supply, a resistor for discharging, which is connected in parallel to the capacitor, and a fourth transistor connected to the first transistor in parallel, the fourth transistor receiving at its gate an a reference voltage for limiting a voltage.

Claims17

Dependent claims

A peak-hold circuit, comprising:

a differential amplifier having first and second transistors as a differential pair, the first transistor receiving an input signal at its gate;
a third transistor connected between a first power supply and an output node connecting a gate of the second transistor, connectivity of the third transistor being controlled by the output of the differential amplifier;
a capacitor for holding a peak voltage, connected between the output node and a second power supply;
a resistor for discharging, which is connected in parallel to the capacitor;
and
a fourth transistor connected to the first transistor in parallel, the fourth transistor receiving at its gate a reference voltage for limiting a voltage.

3 more elements

A received-signal strength indicator, comprising:

a first amplifier circuit having an input terminal outputting a first signal by amplifying an input signal supplied to its input terminal;
a second amplifier circuit outputting a second signal by amplifying the first signal;
a first peak-hold circuit outputting a third signal having a first reference voltage when the voltage of the first signal is equal to or lower than the first reference voltage, and holding a peak value of the first signal and outputting a third signal having the peak value of the first signal when the voltage of the first signal is higher than the first reference voltage;
a second peak-hold circuit outputting a fourth signal having a second reference voltage when the voltage of the second signal is higher than the second reference voltage, which is higher than the first reference voltage, and holding a peak value of the second signal and outputting a fourth signal having the peak value of the second signal when the voltage of the second signal is equal to or lower than the second reference voltage;
and
an adder circuit adding the voltages of the third and the fourth signals, and outputting an output signal corresponding to a strength of the input signal.

3 more elements

A received-signal strength indicator, comprising:

a first-stage amplifier circuit having an input terminal outputting a first signal by amplifying an input signal supplied to its input terminal;
an intermediate-stage amplifier circuit outputting a second signal by amplifying the first signal;
a final-stage amplifier circuit outputting a third signal by amplifying the second signal;
a first peak-hold circuit outputting a fourth signal having a first reference voltage when the voltage of the first signal is equal to or lower than the first reference voltage, and holding a peak value of the first signal and outputting a fourth signal having the peak value of the first signal when the voltage of the first signal is higher than the first reference voltage;
a second peak-hold circuit outputting a fifth signal having a second reference voltage when the voltage of the third signal is higher than the second reference voltage, which is higher than the first reference voltage, and holding a peak value of the third signal and outputting a fifth signal having the peak value of the third signal when the voltage of the third signal is equal to or lower than the second reference voltage;
a third peak-hold circuit outputting a sixth signal having a third reference voltage when the voltage of the second signal is equal to or lower than the third reference voltage, which is higher than the first reference voltage but lower than the second reference voltage, outputting a sixth signal having a fourth reference voltage when the voltage of the second signal is higher than the fourth reference voltage, which is higher than the third reference voltage but lower than the second reference voltage, and holding a peak value of the second signal and outputting a sixth signal having the peak value of the second signal when the voltage of the second signal is equal to or lower than the fourth reference voltage, but higher than the third reference voltage;
and
an adder circuit adding the voltages of the fourth, the fifth and the sixth signals, and outputting a output signal corresponding to a strength of the input signal.

5 more elements

Dependencies are inferred from the claim text.

Peak-hold circuit and signal strength indicator using the peak-hold circuit

Life of this patent

Peak-hold circuit and signal strength indicator using the peak-hold circuit

Life of this patent

Abstract

Claims17