High speed flip-flop
AssigneeSamsung Electronics Co., Ltd.
InventorsMin-Su KIM, Bai-Sun KONG
Life of this patent
Estimating the term…
Abstract
A flip-flop circuit includes a precharging circuit which precharges a first circuit node in response to a first pulse signal and an estimation circuit that receives an input signal and a second pulse signal. The estimation circuit discharges the voltage from the first node in response to the input signal on activation of the second pulse signal. The first pulse signal is synchronized to a clock signal and the second pulse signal is delayed from the first pulse signal.
Claims31
A flip-flop comprising:
- a precharging circuit connected to a first node, said precharging circuit configured to precharge said first node in response to a first pulse signal, said first pulse signal synchronized to a clock signal;
- and
- an estimation circuit connected to said first node, said estimation circuit configured to receive an input signal and a second pulse signal, said estimation circuit discharging a voltage associated with said first node in response to said input signal upon activation of said second pulse signal, said second pulse signal delayed by a time period from said first pulse signal.
A flip-flop comprising:
- a precharging circuit connected to a first node, said precharging circuit configured to precharge said first node in response to a first pulse signal, said first pulse signal synchronized to a clock signal;
- a discharging circuit connected to a second node and configured to discharge said second node in response to a second pulse signal, said second pulse signal delayed by a time period from said first pulse signal;
- and
- an input circuit connecting the first node to the second node in response to an input signal.
A flip-flop comprising:
- a first transistor connected between a power source voltage and a first node, said first transistor controlled by a first pulse signal;
- a second transistor connected between said first node and a second node, said second transistor controlled by an input signal;
- and
- a third transistor connected between said first node and a ground voltage, said third transistor controlled by a second pulse signal, said first and second pulse signals generated in sync with a clock signal.
An electronic circuit comprising:
- a pulse generator configured to generate a first and second pulse signals, said first pulse signal in sync with a clock signal, said second pulse signal delayed with respect to said first pulse signal;
- and
- a flip-flop transferring an input signal to a first node in response to said first and second pulse signals, said flip flop comprising:
- a precharging circuit connected to said first node and configured to precharge said first node in response to said first pulse signal;
- and
- an estimation circuit connected to said to said first node, said estimation circuit configured to receive said input signal and said second pulse signal, said estimation circuit further configured to selectively discharge the voltage associated with said first node in response to the input signal on activation of said second pulse signal.
A method of operating a flip-flop circuit comprising:
- precharging a first node to a first level in response to a first pulse signal;
- selectively discharging the first node in response to a second pulse signal and an input signal;
- generating the first pulse signal in sync with a clock signal;
- and
- generating the second pulse signal by delaying and inverting the first pulse signal.
Dependencies are inferred from the claim text.