De-Glitch Circuit
AssigneeSanDisk Corporation
InventorsDarmin Jin, Brian Cheung
Life of this patent
Estimating the term…
Abstract
A digital logic circuit and method for de-glitching an input signal. The circuit removes distortion that occurs during a “de-glitching” time period that follows each transition of the input signal from 0 to 1 or from 1 to 0. The circuit can remove such distortion from the input signal without substantially delaying the input signal. Specifically, the delay interposed can be much less than the duration of the de-glitching time period. One embodiment includes first and second Set-Reset flip-flops each having an input connected to receive the input signal and having an output connected to a majority circuit. A delay circuit also receives the input signal and provides an output to the majority circuit. Other embodiments replace the majority circuit with a circuit including logic gates.
Claims20
A de-glitch circuit having an input and an output, comprising:
- a 3-input majority circuit having first, second and third inputs and having an output connected to the output of the de-glitch circuit;
- a first Set-Reset flip-flop having a first Set input, a first Reset input, and a first flip-flop output, wherein the first flip-flop output is connected to the first input of the majority circuit, and wherein the first Set input is connected to the input of the de-glitch circuit;
- a second Set-Reset flip-flop having a second Set input, a second Reset input, and a second flip-flop output, wherein the second flip-flop output is connected to the second input of the majority circuit, and wherein the second Set input is connected to the input of the de-glitch circuit;
- a first delay circuit having an output and having an input connected to the input of the de-glitch circuit;
- a second delay circuit having an input connected to the output of the first delay circuit and having an output connected to the third input of the majority circuit;
- and
- a one-shot circuit having an input connected to the output of the first delay circuit and having an output connected to the first Reset input and the second Reset input.
A de-glitch circuit having an input and an output, comprising:
- a NOR gate having first and second inputs and having an output connected to the output of the de-glitch circuit;
- an AND gate having first and second inputs and having an output connected to the second input of the NOR gate;
- a first Set-Reset flip-flop having a first Set input, a first Reset input, and a first flip-flop output, wherein the first flip-flop output is connected to the first input of the NOR gate, and wherein the first Set input is connected to the input of the de-glitch circuit;
- a second Set-Reset flip-flop having a second Set input, a second Reset input, and a second flip-flop output, wherein the second flip-flop output is connected to the first input of the AND gate, and wherein the second Set input is connected to the input of the de-glitch circuit;
- a first delay circuit having an output and having an input connected to the input of the de-glitch circuit;
- a second delay circuit having an input connected to the output of the first delay circuit and having an output connected to the second input of the AND gate;
- and a one-shot circuit having an input connected to the output of the first delay circuit and having an output connected to the first Reset input and the second Reset input.
Dependencies are inferred from the claim text.