Semiconductor memory device with ability to effectively adjust operation time for on-die termination

A semiconductor memory device comprising:

• a first latency control unit for producing a normal ODT driving enable signal by delaying an ODT operation signal from an external circuit during a first latency;
• a second latency control unit for producing a write ODT driving enable signal by delaying a write command signal, which is produced in response to a write command, during a second latency;
• a control signal generating unit for producing control signals to control a change of waveform of the ODT driving enable signal;
• a first trimming control unit for changing the waveform of the normal ODT driving enable signal in response to the control signals, thereby outputting a normal ODT driving signal;
• a second trimming control unit for changing the waveform of the write ODT driving enable signal in response to the control signals, thereby outputting a write ODT driving signal;
• and
• a termination circuit for connecting a normal termination resistance to an impedance adjusting node in response to the normal ODT driving signal and for disconnecting the normal termination resistance from the impedance adjusting node and connecting a write termination resistance to the impedance adjusting node in response to the write ODT driving signal.

A semiconductor memory device comprising:

• a latency control unit for producing an ODT driving enable signal by delaying an ODT operation signal from an external circuit during a predetermined latency;
• an ODT signal delay unit for delaying the ODT driving enable signal by an amount of delay which is correspondent to control signals;
• a pulse width adjusting unit for changing waveform of the delayed ODT driving enable signal from the ODT signal delay unit, thereby outputting the ODT driving signal;
• and
• a termination circuit for connecting a termination resistance to an impedance adjusting node in response to the ODT driving signal.

A semiconductor memory device comprising:

• a first latency control unit for producing a normal ODT driving enable signal by delaying an ODT operation signal from an external circuit during a first latency;
• a second latency control unit for producing a write ODT driving enable signal by delaying a write command signal, which is produced in response to a write command, during a second latency;
• a normal ODT signal delay unit for delaying the normal ODT driving enable signal by an amount of delay which is correspondent to control signals;
• a normal pulse width adjusting unit for changing a pulse width of the delayed normal ODT driving enable signal from the normal ODT signal delay unit, thereby outputting a normal ODT driving signal;
• a write ODT signal delay unit for delaying the write ODT driving enable signal by an amount of delay which is correspondent to control signals;
• a write pulse width adjusting unit for chanting a pulse width of the delayed write ODT driving enable signal from the write ODT signal delay unit, thereby outputting a write ODT driving signal;
• and
• a termination circuit for connecting a normal termination resistance to an impedance adjusting node in response to the normal ODT driving signal and for disconnecting the normal termination resistance from the impedance adjusting node and connecting a write termination resistance to the impedance adjusting node in response to the write ODT driving signal.

A method for driving a semiconductor-memory device comprising:

• producing an ODT driving enable signal by delaying an ODT operation signal from an external circuit during a predetermined latency;
• producing control signals to control a change of waveform of the ODT driving enable signal;
• changing the waveform of the ODT driving enable signal in response to the control signals, thereby outputting a ODT driving signal;
• and
• connecting a termination resistance to an impedance adjusting node in response to the ODT driving signal.

A method for driving a semiconductor memory device comprising:

• producing a normal ODT driving enable signal by delaying an ODT operation signal from an external circuit during a first latency;
• producing a write ODT driving enable signal by delaying a write command signal, which is produced in response to a write command, during a second latency;
• producing control signals to control a change of waveform of the ODT driving enable signal;
• changing the waveform of the normal ODT driving enable signal in response to the control signals, thereby outputting a normal ODT driving signal;
• changing the waveform of the write ODT driving enable signal in response to the control signals, thereby outputting a write ODT driving signal;
• connecting a normal termination resistance to an impedance adjusting node in response to the normal ODT driving signal;
• and
• disconnecting the normal termination resistance from the impedance adjusting node and connecting a write termination resistance to the impedance adjusting node in response to the write ODT driving signal.