System and method for testing semiconductor integrated circuit in parallel
AssigneeSamsung Electronics Co., Ltd.
InventorsMin-Gu Kim, Young-Soo An, Ho-Jeong Choi, Jung-Hyeon Kim
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Abstract
A system and method for testing a semiconductor integrated circuit (IC) in parallel includes a probe chuck, a test head, and a test controller. The probe chuck loads a plurality of different types of semiconductor DUTs. The test head provides a plurality of circuit sites to independently and simultaneously test the different types of semiconductor DUTs, and the test controller controls the test head and the probe chuck.
Claims19
A system for testing semiconductor devices in parallel, comprising:
- a probe chuck for loading a plurality of different types of semiconductor DUTs (device under test);
- a test head for providing a plurality of circuit sites to independently and simultaneously test the different types of semiconductor DUTs;
- and
- a test controller for controlling the test head and the probe chuck.
A system for testing semiconductor devices in parallel, comprising:
- a probe chuck loadable with different types of semiconductor DUTs;
- a test head for providing at least two circuit sites that can be used as a single circuit site by combining allocated resources;
- and
- a test controller for controlling the test head and the probe chuck.
A method of testing semiconductor devices in parallel, comprising:
- providing a plurality of different types of semiconductor DUTs;
- selecting at least two different types of test items;
- selecting the different types of semiconductor DUTs arranged at different locations in order to test the test items;
- and
- testing the different types of semiconductor DUTs independently and simultaneously.
Dependencies are inferred from the claim text.