High power semiconductor package

2:

• The high power semiconductor package of claim 1, wherein the insulation substrate is a ceramic substrate.

3:

• The high power semiconductor package of claim 2, wherein the ceramic substrate is formed of Al2O3 or BeO.

4:

• The high power semiconductor package of claim 1, wherein the insulation substrate is formed of a metal nitride.

5:

• The high power semiconductor package of claim 4, wherein the metal nitride is AlN or SiN.

(canceled)

7:

• The high power semiconductor package of claim 1, wherein the interconnection patterns has a thickness in a range from 100 μm to 500 μm.

8:

• The high power semiconductor package of claim 1, wherein the encapsulation member is formed of an epoxy molding compound (EMC).

9:

• The high power semiconductor package of claim 1, wherein the first dimples are formed in an edge portion of the interconnection patterns.

10:

• The high power semiconductor package of claim 1, wherein the first dimples have a maximum diameter in a range from 0.1 mm to 3 mm.

11:

• The high power semiconductor package of claim 1, wherein the first dimples range in depth from 10% to 100% of a thickness of the interconnection patterns.

12:

• The high power semiconductor package of claim 1, wherein the first dimples are arranged at regular intervals in at least one row.

13:

• The high power semiconductor package of claim 1, wherein the encapsulation member fills up the first dimples.

14:

• The high power semiconductor package of claim 1, further comprising a low power semiconductor chip mounted on the first surface of the insulation substrate, the low power semiconductor chip electrically connected with the interconnection patterns so as to drive the power control semiconductor chip.

15:

• The high power semiconductor package of claim 1, wherein the first dimples are formed in the interconnection patterns located on the edge portion of the insulation substrate more densely than in the interconnection patterns located on the center portion of the insulation substrate.

17:

• The high power semiconductor package of claim 16, wherein the insulation substrate is a ceramic substrate.

18:

• The high power semiconductor package of claim 16, wherein the insulation substrate is formed of a metal nitride.

19:

• The high power semiconductor package of claim 16, wherein the interconnection patterns is formed of copper or a copper alloy.

20:

• The high power semiconductor package of claim 16, wherein the interconnection patterns has a thickness in a range from 100 μm to 500 μm.

21:

• The high power semiconductor package of claim 16, wherein the base metal layer is formed of aluminum, an aluminum alloy, copper, or a copper alloy.

22:

• The high power semiconductor package of claim 16, wherein the first dimples are formed in an edge portion of the interconnection patterns.

23:

• The high power semiconductor package of claim 16, wherein the first dimples have a maximum diameter in a range from 0.1 mm to 3 mm.

24:

• The high power semiconductor package of claim 16, wherein the first dimples range in depth from 10% to 100% of a thickness of the interconnection patterns.

25:

• The high power semiconductor package of claim 16, further comprising a plurality of second dimples formed in an edge of the bottom surface of the base metal layer.

26:

• The high power semiconductor package of claim 25, wherein the second dimples have a diameter in a range from 0.1 mm to 3 mm.

27:

• The high power semiconductor package of claim 25, wherein the second dimples range in depth from 10% to 100% of a thickness of the base metal layer.

28-31. (canceled)

32:

• The high power semiconductor package of claim 1, wherein the interconnection patterns is formed of copper or a copper alloy.

33:

• The high power semiconductor package of claim 4, wherein the interconnection patterns is formed of copper or a copper alloy.

34:

• The high power semiconductor package of claim 25, wherein the second dimples are arranged at regular intervals in at least one row.

35:

• The high power semiconductor package of claim 25, wherein the encapsulation member fills up the first dimples.

36:

• The high power semiconductor package of claim 16, further comprising a low power semiconductor chip mounted on the first surface of the insulation substrate, the low power semiconductor chip electrically connected with the interconnection patterns so as to drive the power control semiconductor chip.

37:

• The high power semiconductor package of claim 16, wherein the first dimples are formed in the interconnection patterns located on the edge portion of the insulation substrate more densely than in the interconnection patterns located on the center portion of the insulation substrate.