Method and structure for reduction of soft error rates in integrated circuits

A structure, comprising:

• an integrated circuit, said integrated circuit comprising:
• a semiconductor substrate;
• and
• a stack of one or more wiring levels on a top surface of said substrate, said stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, said lowermost wiring level nearer said semiconductor substrate than said uppermost wiring level;
• and
• an alpha particle blocking layer on a top surface of said uppermost wiring level of said one or more wiring levels, said blocking layer comprising metal wires and a dielectric material, a combination of the thickness of said stack of wiring levels and a volume percent of metal wires in said stack of wiring levels, and a thickness of said blocking layer and a volume percent of metal wires in said blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking said blocking layer from penetrating into said substrate.

A method, comprising:

• providing a test device, said test device comprising:
• a semiconductor substrate;
• and
• a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, said lowermost wiring level on a top surface of said substrate;
• selecting an energy of alpha particles of a given energy to be stopped from penetrating through said stack of one or more wiring levels;
• bombarding said semiconductor substrate with a flux of said alpha particles of said selected energy;
• and
• determining a combination of a thickness of a blocking layer and a volume percent of metal wires in said blocking layer sufficient to stop a predetermined percentage of alpha particles of said maximum energy striking a top surface of said blocking layer from penetrating through said stack of one or more wiring levels.

A method, comprising:

• providing a device design, said test design comprising:
• a semiconductor substrate;
• and
• a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, said lowermost wiring level on a top surface of said substrate;
• selecting alpha particles of a given energy;
• and
• mathematically simulating bombardment of said device with a flux of said alpha particles of said selected energy.