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US 2008/0164561 A1Published application
Shallow trench isolation process utilizing differential liners
AssigneeAdvanced Micro Devices, Inc.
InventorSrinath Krishnan
Life of this patent
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Abstract
A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce strain in the substrate.
Claims20
An integrated circuit, comprising:
- a first doped region of a substrate;
- a second doped region of the substrate;
- a first type liner on a first side wall of a trench, the trench being between the first doped region and the second doped region and the first side wall being associated with the first doped region;
- and
- a second type liner on a second side wall of the trench, the second side wall being associated with the second doped region, wherein the first type liner is disposed directly on the first sidewall and the second type liner is disposed directly on the second side wall.
2 more elements
An integrated circuit, comprising:
- a base layer of a substrate;
- a buried insulative layer of a substrate disposed on the base layer;
- a first doped region formed on a first portion of the buried insulative layer;
- a second doped region formed on a second portion of the buried insulative layer;
- a first type liner on a first side wall of a trench, the trench being between the first doped region and the second doped region and the first side wall being associated with the first doped region;
- and
- a second type liner on a second side wall of the trench, the second side wall being associated with the second doped region, wherein the first type liner is disposed directly on the first sidewall and the second type liner is disposed directly on the second side wall.
4 more elements
Dependencies are inferred from the claim text.