Isolation structures for CMOS image sensor chip scale packages

A CMOS image sensor chip scale package, comprising:

• a transparent substrate configured as a support structure for the package, the transparent substrate comprising a first cutting edge and a second cutting edge;
• a CMOS image sensor die with a die circuitry attached on the transparent substrate;
• an encapsulant on the substrate encapsulating the CMOS image sensor die;
• a connection extending from the die circuitry to a plurality of terminal contacts for the package on the encapsulant, the connection exposed by the first cutting edge;
• and
• an isolation structure on the first cutting edge passivating the exposed connection and co-planar with the second cutting edge.

A method for fabricating a CMOS image sensor chip scale package, comprising:

• providing a transparent substrate with two adjacent CMOS image sensor dies mounted thereon and an encapsulant encapsulating each CMOS image sensor die, wherein a connection extends between both the CMOS image sensor dies and connect to a plurality of terminal contacts for the package on the encapsulant;
• cutting the transparent substrate into a predetermined depth creating a trench to separate and expose the connection corresponding to each CMOS image sensor die;
• filling an isolation structure into the trench passivating the exposed connection;
• and
• cutting the transparent substrate to separate CMOS image sensor packages.