Embedded stressed nitride liners for cmos performance improvement
AssigneeInternational Business Machines Corporation
InventorsDureseti Chidambarrao, Omer H. Dokumaci
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Abstract
The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner providing a stress to a device channel underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 275 MPa to about 450 MPa.
Claims13
1-2. (canceled)
The structure of claim 11 wherein said nitride liner comprises Si3N4.
The structure of claim 11 wherein said nitride liner has a thickness ranging from about 40 nm to about 100 nm.
The structure of claim 11 wherein said stress is produced in a portion of said device channel positioned about 5 nm or less below said gate region.
The structure of claim 11 wherein said mesa top surface is vertically offset from said recessed surfaces by a depth ranging from about 10 nm to about 80 nm.
The structure of claim 11 wherein the substrate comprises Si, bulk Si, single crystal Si, polycrystalline Si, SiGe, amorphous Si, silicon-on-insulator (SOI), SiGe-on-insulator (SGOT), annealed poly Si, poly Si line structures, GaAs, InAs, or a combination thereof.
The structure of claim 11 wherein said stress on said device channel, is a longitudinal stress ranging from about 250 MPa to about 450 MPa.
The structure of claim 11 wherein said sidewall spacer has a width ranging from about 20 nm to about 60 nm.
(canceled)
A semiconducting device comprising:
- a semiconductor substrate having a mesa portion and recessed surfaces, wherein said mesa portion contains a mesa top surface and mesa sidewalls located above and adjoined to said recessed surfaces, and wherein said mesa top surface is vertically offset from said recessed surfaces;
- a singled gated transistor comprising a gate region including a gate dielectric and a gate electrode, wherein said gate dielectric abuts said mesa top surface and is disjoined from said recessed surfaces and said mesa sidewalls;
- sidewall spacers abutting said mesa top surface, wherein outer surfaces of said sidewall spacers are aligned to said mesa sidewalls;
- source and drain regions located under and aligned to said recessed surfaces and substantially aligned to said sidewall spacers;
- and
- a nitride liner abutting said sidewall spacers, said mesa sidewalls, and said recessed surfaces and not abutting said mesa top surface, wherein said nitride liner provides a longitudinal stress to a device channel underlying said gate region in said mesa portion of said semiconductor substrate.
Dependencies are inferred from the claim text.