Dual interlayer dielectric stressor integration with a sacrificial underlayer film stack
AssigneeFreescale Semiconductor, Inc.
InventorsDharmesh Jawarani, Ross E. Noble, David C. Wang
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Abstract
A method for making a semiconductor device is provided by (a) providing a substrate (203) having first (205) and second (207) gate structures thereon; (b) forming an underlayer (231) over the first and second gate structures; (c) removing the underlayer from the first gate structure; (d) forming a first stressor layer (216) over the first and second gate structures; and (e) selectively removing the first stressor layer from the second gate structure through the use of a first etch which is selective to the underlayer.
Claims20
A method for making a semiconductor device, comprising:
- providing a substrate having first and second gate structures thereon;
- forming an underlayer over the first and second gate structures;
- removing the underlayer from the first gate structure;
- forming a first stressor layer over the first and second gate structures;
- and
- removing the first stressor layer from the second gate structure through the use of a first etch which uses the underlayer as an etch stop layer.
A method for making a semiconductor device, comprising:
- providing a substrate having first and second gate structures thereon, wherein the first gate structure is disposed in an NMOS region of the device, and wherein the second gate structure is disposed in a PMOS region of the device;
- forming an underlayer over the substrate;
- forming a first layer of stress inducing material over the underlayer;
- masking the device such that the first gate structure is exposed and the second gate structure is covered;
- and
- removing the first layer of stress inducing material from the second gate structure with a first wet etch which is selective to the underlayer.
A semiconductor device, comprising:
- a substrate having first and second gate structures thereon, wherein the first gate structure is disposed in an PMOS region of the device, and wherein the second gate structure is disposed in a NMOS region of the device;
- an underlayer disposed over the substrate;
- and
- a first layer of stress inducing material disposed over the underlayer.
Dependencies are inferred from the claim text.