Integrated circuits with stress memory effect and fabrication methods thereof

A method for fabricating a semiconductor device with selective stress memory effect thereon, comprising:

• providing a semiconductor substrate with a first region and a second region, each of the first region and the second region having a first doped region and a second doped region separated by an insulation;
• forming a PMOS transistor on the first doped region layer and an NMOS transistor on the second doped region;
• forming a silicon oxide layer covering the NMOS transistor and the PMOS transistor;
• forming a silicon nitride layer on the silicon oxide layer;
• thinning part of the silicon nitride layer overlying the PMOS transistor;
• removing a portion of the silicon oxide layer and the silicon nitride layer over the second region;
• and
• silicidizing the PMOS transistor and the NMOS transistor over the second region.

A method for fabricating a semiconductor device with selective stress memory effect thereon, comprising:

• providing a semiconductor substrate with a first region and a second region, each of the first region and the second region having a first doped region and a second doped region separated by an insulation;
• forming a PMOS transistor on the first doped region layer and an NMOS transistor on the second doped region;
• forming a silicon oxide layer covering the NMOS transistor and the PMOS transistor over both the first and the second regions;
• forming a silicon nitride layer on the silicon oxide layer;
• thinning part of the silicon nitride layer overlying the PMOS transistor over both the first and the second regions;
• annealing the semiconductor substrate, thereby inducing different stress on the PMOS transistor and the NMOS transistor respectively;
• removing the silicon oxide layer and the silicon nitride layer over the second region;
• and
• silicidizing the PMOS transistor and the NMOS transistor over the second region.