Self-aligned metal-semiconductor alloy and metallization for sub-lithographic source and drain contacts

A double-gate field effect transistor (FET) comprising:

• a single-crystal Si channel;
• a top-gate and a back-gate on either side of the Si channel for controlling the current through the Si channel;
• a source region and a drain region adjacent to the Si channel, said source and drain regions have a lateral size defined by a footprint of a spacer;
• a raised source and raised drain formed on top of said source and drain;
• silicide regions over the source region, the drain region, and the top-gate;
• buried metal lines connecting to an edge of silicide regions;
• and
• metal studs connecting to the buried metal lines.

A method of forming a double-gate FET comprising:

• forming a structure including a single-crystal semiconductor film with a gate dielectric on its top and bottom surfaces, a bottom-gate, and a top-gate with dielectric sidewall spacers;
• forming sacrificial spacers adjacent to said top-gate;
• defining sub-lithographic source and drain regions by etching unmasked regions of said single-crystal semiconductor film;
• providing a first planarized dielectric on said structure;
• recessing said first planarized dielectric below an upper surface of said top-gate;
• removing said sacrificial spacers to expose top surfaces of said sub-lithographic defined source and drain regions;
• forming a metal-semiconductor alloy on said exposed surfaces of said source and drain regions utilizing a metal film, wherein a portion of said metal film which does not form a metal-semiconductor alloy is located atop the first planarized dielectric;
• depositing a second planarized dielectric over at least said metal-semiconductor alloy;
• and
• etching selectively said metal over said dielectric sidewall spacers.