Method of trimming a hard mask layer, method for fabricating a gate in a mos transistor, and a stack for fabricating a gate in a mos transistor

A method of forming a gate of a MOS transistor, comprising:

• providing a substrate;
• forming a dielectric layer, a conductive layer and a hard mask layer on said substrate;
• forming a multi-layer stack comprising at least a top photo resist layer, a silicon photo resist layer, and a bottom photo resist layer on said hard mask layer;
• patterning said top photo resist layer;
• etching said silicon photo resist layer by using said patterned top photo resist layer as an etching mask to pattern said silicon photo resist layer to form a first opening of a first width on the bottom thereof;
• removing said top photo resist layer;
• etching said bottom photo resist layer sequentially by using said patterned silicon photo resist layer as an etching mask;
• etching said hard mask layer sequentially by using said patterned bottom photo resist layer as an etching mask to form a second opening of said first width;
• trimming said hard mask layer to make said second opening with a second width larger than said first width;
• and
• etching said conductive layer by using said hard mask layer with said second opening as an etching mask to form a gate.