Semiconductor device having three-demensional transistor and manufacturing method thereof
AssigneeElpida Memory, Inc.
InventorShigeru Sugioka
Life of this patent
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Abstract
A semiconductor device includes an active region surrounded by an element isolation region; a gate electrode crossing the active region; and at least one slit provided at a boundary portion between the element isolation region and the active region and having a first region covered with the gate electrode and second region not covered with the gate electrode; wherein the first region of the slit is embedded with a conductive material which is the same as that of the gate electrode, and at least an upper part of a second region of the slit is embedded with an insulation material.
Claims16
A semiconductor device comprising:
- an active region surrounded by an element isolation region, at least one slit being provided at a boundary portion between the element isolation region and the active region;
- and
- a gate electrode crossing the active region and the slit,
- wherein the slit has a first region covered with the gate electrode and a second region not covered with the gate electrode, the first region of the slit is embedded with a conductive material which is the same as that of the gate electrode, and at least an upper part of the second region of the slit is embedded with an insulation material.
A method of manufacturing a semiconductor device comprising:
- a first step for forming an active region surrounded by an element isolation region;
- a second step for forming a slit on a boundary portion between the element isolation region and the active region;
- a third step for depositing a gate electrode material on at least the active region and the inside of the slit;
- a fourth step for patterning the gate electrode material to form a gate electrode crossing the active region and to form a cavity in a part of the slit;
- and
- a fifth step for embedding the cavity with an insulation material.
Dependencies are inferred from the claim text.