Semiconductor device
OwnerSung-Jin Kiminventor
Life of this patent
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Abstract
A semiconductor device having spacer patterns formed at the sidewalls of gate electrodes and a method of fabricating the same are disclosed. The semiconductor device includes a gate pattern, including a plurality of gate electrodes, formed on a semiconductor substrate, a barrier insulation layer formed on the entire surface of the substrate including the gate pattern, and spacer patterns formed at opposite sidewall regions of the respective gate electrodes surrounded by the barrier insulation layer such that the spacer patterns have a height less than that of the respective gate electrodes.
Claims18
A device, comprising:
- a gate pattern, having a plurality of gate electrodes, formed over a semiconductor substrate;
- a barrier insulation layer formed over a surface of the substrate including the gate pattern;
- and
- spacer patterns formed at opposite sidewall regions of respective gate electrodes and surrounded by the barrier insulation layer, wherein the spacer patterns have a height less than that of the respective gate electrodes.
A method, comprising:
- forming a gate pattern, including a plurality of gate electrodes, over a semiconductor substrate;
- forming a barrier insulation layer over a surface of the substrate including the gate pattern;
- forming a spacer insulation layer over the surface of the substrate where the barrier insulation layer is formed;
- and
- forming spacer patterns at opposite sidewall regions of the respective gate electrodes such that the spacer patterns have a height less than that of the respective gate electrodes.
A device, comprising:
- a plurality of gate electrodes over a semiconductor substrate, each gate electrode comprising a tunnel insulation layer, a floating gate, an intergate dielectric layer, a control gate electrode, and a capping insulation layer;
- a barrier insulation layer formed over a surface of the substrate including the gate pattern;
- and
- spacer patterns formed at opposite sidewall regions of respective gate electrodes and surrounded by the barrier insulation layer.
Dependencies are inferred from the claim text.