Semiconductor memory devices performing erase operation using erase gate and methods of manufacturing the same

A semiconductor memory device, comprising:

• at least one erase gate formed on an insulation layer;
• and
• a charge trap layer formed on the at least one erase gate, wherein the charge trap layer stores a first charge transfer medium having a first polarity and the at least one erase gate includes a second charge transfer medium having a second polarity opposite to the first polarity,
• wherein, in an erase mode, the second charge transfer medium migrates to the charge trap layer causing the first charge transfer medium to combine with the second charge transfer medium.

A method of manufacturing a semiconductor memory device, comprising:

• forming at least one oxidation region on a top region of a semiconductor substrate;
• forming at least one erase gate on the at least one oxidation region;
• and
• forming a charge trap layer on the at least one erase gate,
• wherein the charge trap layer stores a first charge transfer medium having a first polarity and the at least one erase gate includes a second charge transfer medium having a second polarity opposite to the first polarity.

A method of manufacturing a semiconductor memory device, comprising:

• forming at least one erase gate on an insulation layer;
• and
• forming a charge trap layer on the at least one erase gate, wherein the charge trap layer stores a first charge transfer medium having a first polarity and the at least one erase gate stores a second charge transfer medium having a second polarity opposite to the first polarity,
• wherein, in an erase mode, the second charge transfer medium in the at least one erase gate migrates to the charge trap layer causing the first charge transfer medium stored in the charge trap layer to combine with the second charge transfer medium.