Memory devices and methods of manufacturing the same

A memory device comprising:

• a tunnel insulation layer pattern on a semiconductor substrate;
• a composite layer pattern on the tunnel insulation layer pattern, the composite layer pattern configured to have an energy band gap lower than that of the tunnel insulation layer pattern and an energy band gap gradient according to a height from the tunnel insulation layer pattern;
• a blocking layer pattern on the composite layer pattern;
• a gate electrode on the blocking layer pattern;
• and
• a source/drain region at an upper portion of the semiconductor substrate, the upper portion being adjacent to the tunnel insulation layer pattern.

A method of manufacturing a memory device, the method comprising:

• forming a first tunnel insulation layer on a semiconductor substrate;
• forming a second tunnel insulation layer on the first tunnel insulation layer, the second tunnel insulation layer configured to have an energy band gap lower than that of the first tunnel insulation layer;
• forming a charge trapping layer on the second tunnel insulation layer;
• forming a blocking layer on the charge trapping layer;
• forming a gate conductive layer on the blocking layer;
• forming a first tunnel insulation layer pattern, a second tunnel insulation layer pattern, a charge trapping layer pattern, a blocking layer pattern and a gate electrode stacked on the semiconductor substrate by patterning the gate conductive layer, the blocking layer, the charge trapping layer, the second tunnel insulation layer and the first tunnel insulation layer;
• and
• forming a source/drain region at an upper portion of the semiconductor substrate by implanting impurities onto the semiconductor substrate, the upper portion being adjacent to the first tunnel insulation layer pattern.