Thin film transistor, method of fabricating the same, and flat panel display device including the same

A method of fabricating a thin film transistor, comprising:

• forming a polycrystalline silicon layer on a substrate;
• patterning the polycrystalline silicon layer to form a semiconductor layer;
• forming a gate insulating layer on the entire surface of the substrate including the semiconductor layer;
• forming a gate electrode on the gate insulating layer above the channel region;
• performing an ion doping process on the semiconductor layer to form source and drain regions, high resistance regions, connection regions, and a channel region;
• forming an interlayer insulating layer on the entire surface of the substrate including the gate electrode;
• and
• forming source and drain electrodes connected, respectively, to the source and drain regions on the interlayer insulating layer.

A flat panel display device comprising:

• a substrate;
• a semiconductor layer on the substrate and comprising source and drain regions, high resistance regions smaller than the source and drain regions, a channel region, and connection regions between respective said high resistance regions and the channel region;
• a gate insulating layer on the semiconductor layer;
• a gate electrode on the gate insulating layer above the channel region;
• an interlayer insulating layer on the gate electrode;
• source and drain electrodes on the interlayer insulating layer and electrically connected to the source and drain regions, respectively;
• and
• a display element coupled with the source electrode or the drain electrode, wherein the display element is adapted to display an image in accordance with voltages applied at the gate electrode and the source and drain electrodes.

A thin film transistor comprising:

• a substrate;
• a semiconductor layer on the substrate and comprising source and drain regions, high resistance regions having a smaller width than the source and drain regions, a channel region, and connection regions between respective said high resistance regions and the channel region;
• a gate insulating layer on the semiconductor layer;
• a gate electrode on the gate insulating layer above the channel region;
• an interlayer insulating layer on the gate electrode;
• and
• source and drain electrodes on the interlayer insulating layer and electrically connected to the source and drain regions, respectively.