Chip stack with precision alignment, high yield assembly and thermal conductivity
AssigneeInternational Business Machines Corporation
InventorJohn U. Knickerbocker
Life of this patent
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Abstract
A method for fabricating a device adapted for precision aligning integrated circuits having small-scale architecture in a stack, the method includes obtaining dimensions of the integrated circuits; fabricating a precision guide using the dimensions; and fabricating alignment fiducials into at least one of the precision guide and a carrier wafer. A method for placing integrated circuits having small-scale architecture into a stack, the method includes selecting a device adapted for precision aligning the integrated circuits into the stack and precision aligning the integrated circuits into the stack.
Claims14
A method for fabricating a device adapted for precision aligning integrated circuits having small-scale architecture in a stack, the method comprising:
- obtaining dimensions of the integrated circuits;
- fabricating a precision guide using the dimensions;
- and
- fabricating alignment fiducials into at least one of the precision guide and a carrier wafer.
A method for placing integrated circuits having small-scale architecture into a stack, the method comprising:
- selecting a device adapted for precision aligning the integrated circuits into the stack and
- precision aligning the integrated circuits into the stack.
A device adapted for stacking a plurality of integrated circuits, the device comprising:
- at least one alignment feature adapted for precision aligning each integrated circuit having a small-scale architecture, wherein the alignment features comprise a precision guide comprising a loading edge and at least one cavity, each cavity comprising at least one precision edge;
- and alignment fiducials comprising at least one of etched features on a semiconductor substrate and alignment pins.
Dependencies are inferred from the claim text.