Trench structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels

A method of fabricating an integrated circuit chip, comprising:

• forming a first pad layer on a top surface of a semiconductor substrate;
• forming a hardmask layer on a top surface of said pad layer;
• etching an opening in said hardmask layer, said top surface of said pad layer exposed in a bottom of said opening;
• locating a first trench in a first position on said substrate relative to a floor plan layout of said integrated circuit chip and etching said first trench through said pad layer into said substrate;
• removing said hardmask layer and said first pad layer;
• forming a second pad layer on said top surface of said substrate and on sidewalls and a bottom surface of said first trench;
• locating one or more second trenches in respective one or more second positions on said substrate relative to said floor plan layout of said integrated circuit chip and etching said one or more second trenches through said pad layer into said substrate;
• at least partially filling said first trench and completely filling said one or more second trenches with an insulator;
• and
• removing said insulator from said first trench.

An integrated circuit structure, comprising:

• a semiconductor substrate;
• an electron beam alignment target positioned in a first location in said substrate, said first location defined in a floor plan design of said integrated circuit, said electron beam alignment target comprising a first trench formed in said substrate;
• an optical alignment target in said substrate, said optical alignment target positioned in a second location relative in said substrate, said second location defined in said floor plan design of said integrated circuit, said optical alignment target comprising a second trench formed in said substrate;
• a layer on said substrate;
• a first opening in said layer positioned in a third location, said third location defined in said floor plan design of said integrated circuit;
• and
• a second opening in said layer positioned in a fourth location, said fourth location defined in said floor plan design of said integrated circuit.

A method, comprising:

• forming an electron beam alignment target in a substrate;
• forming an optical alignment target in said substrate after forming said electron beam alignment target, said optical alignment target positioned in a predetermined location in said substrate relative to a location of said electron beam alignment target in said substrate;
• forming a photoresist layer on said substrate;
• aligning a photomask to either said optical alignment target or to said electron beam alignment target, said photomask having a first pattern of clear and opaque regions representing a first set of features of a fabrication level of an integrated circuit;
• exposing said photoresist layer to actinic radiation through said photomask to form an exposed photoresist layer having exposed and unexposed regions, said opaque regions substantially blocking said actinic radiation and said clear regions substantially transmitting said actinic radiation;
• developing said exposed photoresist layer to transfer said first pattern to said exposed photoresist layer;
• forming a layer of electron beam resist on said substrate;
• locating a home position of an electron beam relative to said location of said electron beam alignment target;
• exposing said electron beam resist to said electron beam in a second pattern to form an exposed electron beam resist layer having exposed and unexposed regions, said second pattern representing a second set of said features of said fabrication level of said integrated circuit;
• and
• developing said exposed electron beam resist layer to transfer said second pattern to said exposed electron beam layer.