Semiconductor device, and method of manufacturing same
AssigneeDongbu HiTek Col, Ltd.
InventorMin Hyung LEE
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Abstract
A semiconductor device, and method for manufacturing a device with selective copper plating in a deep via. The method comprises etching a plurality of deep trenches in the surface of wafer, sequentially forming an insulating layer, a copper anti-diffusion layer, a metal layer, and a copper seed layer over the surface and deep trenches of the wafer, performing a first planarization process in order to remove the copper seed layer on the surface of wafer while retaining the copper seed layer in the deep trenches of the wafer, and forming a plurality of via patterns by copper plating the copper seed layer remaining in the deep trenches of the wafer.
Claims20
A method of manufacturing a semiconductor device comprising:
- forming a plurality of deep trenches in a surface of a wafer using an etching process;
- sequentially forming an insulating layer, a copper anti-diffusion layer, a metal layer, and a copper seed layer over the deep trenches and surface of the wafer;
- performing a first planarization process on the copper seed layer in order to remove the copper seed layer from the surface of the wafer while retaining the copper seed layer in the deep trenches of the wafer;
- and
- forming a plurality of via patterns by performing a copper plating process on the copper seed layer remaining in the deep trenches of the wafer.
A semiconductor device comprising:
- a plurality of deep trenches formed in a surface of a wafer using an etching process;
- an insulating layer, a copper anti-diffusion layer, a metal layer, and a copper seed layer formed sequentially over the deep trenches and surface of the wafer;
- and
- a plurality of copper via patterns formed using copper plating process on the copper seed layer;
- wherein the copper seed layer is removed from the surface of the wafer while being retained in the deep trenches of the wafer before the copper plating process is performed, such that the copper via pattern forms only over the deep trenches of the wafer.
Dependencies are inferred from the claim text.