Metal Line of Semiconductor Device and Method of Manufacturing the Same
AssigneeDongbu HiTek Co., Ltd.
InventorSEUNG HYUN KIM
Life of this patent
Estimating the term…
Abstract
Disclosed are a metal line of a semiconductor device and a method of manufacturing the same. In one embodiment, the metal line includes a first interlayer dielectric layer pattern formed on a lower interconnection structure and having a via hole that exposes a lower interconnection of the lower interconnection structure, a first barrier pattern selectively covering a sidewall of the via hole and the lower interconnection, a second interlayer dielectric layer pattern on the first interlayer dielectric layer pattern and having a trench that exposes the via hole, a second barrier pattern covering an inner wall of the trench and the first barrier pattern, a seed pattern formed on the second barrier pattern, and a copper line formed on the seed pattern.
Claims20
A metal line of a semiconductor device, comprising:
- a first interlayer dielectric layer pattern formed on a lower interconnection and having a via hole exposing the lower interconnection;
- a first barrier pattern selectively provided at a portion of the via hole;
- a second interlayer dielectric layer pattern on the first interlayer dielectric layer pattern and having a trench above the via hole;
- a second barrier pattern in the trench and via hole, the second barrier pattern covering the first barrier pattern;
- a seed pattern formed on the second barrier pattern;
- and
- a copper line formed on the seed pattern.
A method for manufacturing a metal line of a semiconductor device, comprising:
- forming a first interlayer dielectric layer pattern on a lower interconnection and forming a second interlayer dielectric layer pattern on the first interlayer dielectric layer pattern, wherein the first interlayer dielectric layer pattern has a via hole exposing the lower interconnection and the second interlayer dielectric layer pattern has a trench exposing the via hole;
- forming a first barrier pattern selectively covering a sidewall of the via hole and the exposed lower interconnection;
- forming a second barrier pattern on the second dielectric layer pattern including in the trench and via hole, and covering the first barrier pattern;
- forming a seed pattern on the second barrier pattern;
- and
- forming a copper line on the seed pattern.
A method for manufacturing a metal line of a semiconductor device, comprising:
- forming a first interlayer dielectric layer on a lower interconnection structure;
- forming a second interlayer dielectric layer on the first interlayer dielectric layer;
- forming a via hole and a trench exposing a lower interconnection of the lower interconnection structure by patterning the first and second interlayer dielectric layers;
- forming a first barrier layer covering the via hole and the trench;
- performing a blanket etching process for the first barrier layer to form a first barrier layer pattern selectively covering sidewalls of the via hole and the trench;
- forming a second barrier layer pattern in the via hole and the trench including on the first barrier pattern;
- forming a seed pattern on the second barrier layer;
- and
- forming a copper line on the seed pattern.
Dependencies are inferred from the claim text.