Multi-layered metal line of semiconductor device having excellent diffusion barrier and method for forming the same
AssigneeHynix Semiconductor Inc.
InventorsJeong Tae KIM, Baek Mann KIM, Soo Hyun KIM, Young Jin LEE, Dong Ha JUNG
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Abstract
A multi-layered metal line of a semiconductor device has a lower metal line and an upper metal line. The upper metal line includes a diffusion barrier, which is made of a stack of a first WNx layer, a WCyNx layer and a second WNx layer.
Claims29
A multi-layered metal line of a semiconductor device comprising:
- a lower metal line;
- an upper metal line;
- and
- a diffusion barrier formed between the lower and upper metal lines, wherein the diffusion barrier comprises a stack of a first WNx layer, a WCyNx layer, and a second WNx layer.
A method for forming a diffusion barrier layer to prevent diffusion of a metal line in a semiconductor device formed with a multi-layered metal line structure, the method for forming a diffusion barrier comprising the steps of:
- depositing a first WNx layer;
- surface-treating the first WNx layer;
- and
- depositing a second WNx layer on the surface-treated first WNx layer.
A method for forming a multi-layered metal line of a semiconductor device, comprising the steps of:
- forming an interlayer dielectric layer on a semiconductor substrate, the interlayer dielectric layer having a damascene pattern for defining a metal line forming region;
- depositing a first WNx layer on the interlayer dielectric layer including the damascene pattern;
- surface-treating the first WNx layer;
- depositing a second WNx layer on the surface-treated first WNx layer so as to form a diffusion barrier comprising the surface-treated first WNx layer and the second WNx layer;
- and
- forming a wiring metal layer on the diffusion barrier to fill the damascene pattern.
Dependencies are inferred from the claim text.