Stack package having reduced electrical connection length suitable for high speed operations and method of manufacturing the same

A method of manufacturing a stack package, comprising the steps of:

• forming a first mask pattern on a lower surface of a first semiconductor chip having a plurality of first bonding pads formed on an upper surface thereof, wherein the first mask pattern exposes portions of the lower surface of the first semiconductor chip corresponding to the respective locations of the first bonding pads formed on the upper surface;
• etching the exposed portions of the lower surface of the first semiconductor chip to expose the respective first bonding pads so as to define via holes;
• constituting an upper semiconductor chip by removing the first mask pattern from the lower surface of the first semiconductor chip
• forming an insulation layer on an upper surface of a second semiconductor chip having a plurality of second bonding pads formed on the upper surface thereof in the same manner as the first semiconductor chip, wherein the insulation layer are formed to expose the second bonding pads;
• forming a metal seed layer on the exposed second bonding pads and the insulation layer;
• forming a second mask pattern on the metal seed layer wherein the second mask pattern has openings to expose the upper regions of the second bonding pads;
• forming bumps by plating a metal layer to fill the openings of the second mask pattern such that the bumps are formed on the portions of the metal seed layer exposed through the openings of the second mask pattern;
• constituting an lower semiconductor chip by removing the second mask pattern and any portions of the metal seed layer outside the openings of the second mask pattern of the second semiconductor chip;
• and
• attaching the lower semiconductor chip to the lower surface of the upper semiconductor chip such that the bumps of the lower semiconductor chip are inserted into the respective via-holes and are come into the respective first bonding pads.