Stacked semiconductor packages and methods of manufacturing stacked semiconductor packages

Abstract

A stacked semiconductor package may include: a substrate; semiconductor packages stacked on the substrate; an interconnection member formed on edges of the semiconductor packages; and a conductive reinforcement member formed on the interconnection member. Each of the semiconductor packages may include a conductive line. The interconnection member may electrically connect the conductive line of the semiconductor packages to the conductive line of at least one other semiconductor package. A method of manufacturing a stacked semiconductor package may include: forming semiconductor packages; stacking the semiconductor packages on a substrate; forming a mask pattern on the semiconductor packages and the substrate to expose the edges of the semiconductor packages; performing an electroless plating process on the edges of the semiconductor packages to form a seed layer; and performing an electroplating process on the seed layer to form an interconnection member for electrically connecting the conductive lines to each other.

Dependencies are inferred from the claim text.