Stackable integrated circuit package system with recess
AssigneeSTATS ChipPAC, Ltd.
InventorsZigmund Ramirez Camacho, Henry D. Bathan, Jose Alvin Caparas, Lionel Chien Hui Tay
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Abstract
A stackable integrated circuit package system is provided including forming an external interconnect having an interconnect non-recessed portion and an interconnect recessed portion, mounting an integrated circuit die over a paddle that is coplanar with the interconnect recessed portion, and forming an encapsulation having a recess over the external interconnect and the integrated circuit die with the external interconnect exposed at a side of the encapsulation.
Claims20
A stackable integrated circuit package system comprising:
- forming an external interconnect having an interconnect non-recessed portion and an interconnect recessed portion;
- mounting an integrated circuit die over a paddle that is coplanar with the interconnect recessed portion;
- and
- forming an encapsulation having a recess over the external interconnect and the integrated circuit die with the external interconnect exposed at a side of the encapsulation.
A stackable integrated circuit package system comprising:
- forming an external interconnect having an interconnect non-recessed portion and an interconnect recessed portion with an interconnect transition portion in between;
- mounting an integrated circuit die over a paddle that is coplanar with the interconnect recessed portion;
- connecting the integrated circuit die and the external interconnect;
- and
- forming an encapsulation having a recess over the external interconnect and the integrated circuit die with the external interconnect beyond a side of the encapsulation and with the paddle exposed in the recess.
A stackable integrated circuit package system comprising:
- an external interconnect having an interconnect non-recessed portion and an interconnect recessed portion;
- a paddle coplanar with the interconnect recessed portion;
- an integrated circuit die over the paddle;
- and
- an encapsulation having a recess over the external interconnect and the integrated circuit die with the external interconnect exposed at a side of the encapsulation.
Dependencies are inferred from the claim text.