High-stress liners for semiconductor fabrication
AssigneeTexas Instruments Incorporated
InventorsManoj Mehrotra, Stan Ashburn
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Abstract
A method for manufacturing a semiconductor device featuring a high-stress dielectric layer is disclosed. The method involves the deposition of a comparatively thick liner layer that exerts increased strain on an underlying gate and active areas, resulting in enhanced carrier mobility through the transistor and heightened transistor performance. The method also involves the amelioration of fabrication problems that might arise from the deposition of a comparatively thick liner layer by forming such layer with at least a partially direction deposition process. Also disclosed are semiconductor devices manufactured in accordance with the disclosed methods.
Claims20
A method of forming a transistor in a semiconductor substrate, the method comprising:
- forming a transistor gate that spans a plurality of active regions on the semiconductor substrate;
- forming an etch-stop layer over the transistor gate;
- and
- forming a strain-inducing layer liner over the etch-stop layer that is comparatively sensitive to an etch to which the etch-stop layer is comparatively resistant;
- and
- forming a dielectric layer over the strain-inducing layer liner.
A bi-layer liner for a thick strain-inducing layer of a transistor in a semiconductor substrate, the bi-layer liner comprising:
- an etch-stop layer, and
- a strain-inducing layer liner over the etch-stop layer that is comparatively sensitive to an etch to which the etch-stop layer is comparatively resistant.
The method of claim 17, where the etch-stop layer comprises a silicon carbide, and where the strain-inducing layer liner comprises a nitride.
A transistor in a semiconductor substrate, the transistor comprising:
- two transistor gates overlying the semiconductor substrate, and defining a space therebetween;
- an etch-stop layer over the transistor gate;
- a strain-inducing layer liner over the etch-stop layer formed by at least a partially directional deposition process, wherein the strain-inducing layer liner is suffiently thick so as to substantially fill the space between the transistor gates without voiding therein;
- and
- a dielectric layer over the strain-inducing layer liner.
Dependencies are inferred from the claim text.