SRAM and logic transistors with variable height multi-gate transistor architecture

An apparatus comprising:

• a multi-gate SRAM transistor in an integrated circuit having a first non-planar semiconductor body sidewall height and a first non-planar semiconductor body width;
• and
• a multi-gate logic transistor in the integrated circuit having a second non-planar semiconductor body sidewall height and a second width;
• and, wherein the first non-planar semiconductor body sidewall height is greater than the second non-planar semiconductor body sidewall height.

A method of forming a multi-gate SRAM transistor comprising:

• forming first isolation region on a bulk semiconductor substrate adjacent to and planar with a pull-down SRAM transistor semiconductor body;
• forming a second isolation region on the bulk semiconductor substrate adjacent to and planar with a second semiconductor body;
• performing a first etch on both the first isolation region and the second isolation region to expose at least a portion of the sidewalls of both the SRAM transistor semiconductor body and the second transistor semiconductor body;
• masking the second isolation region;
• performing a second etch on the first isolation region to expose an additional portion of the SRAM transistor semiconductor body sidewalls;
• forming a first gate insulator adjacent to the exposed portion of the sidewalls of the pull-down SRAM transistor semiconductor body and forming a second gate insulator adjacent to the exposed portion of the sidewalls of the second transistor semiconductor body;
• forming a first gate electrode adjacent to the first gate insulator and forming a second gate electrode adjacent to the second gate insulator;
• and
• forming a first pair of source/drain regions on opposite sides of the first gate electrode and a second pair of source/drain regions on opposite sides of the second gate electrode.