Tuned tensile stress low resistivity slot contact structure for n-type transistor performance enhancement
AssigneeIntel Corporation
InventorsKevin J. Fischer, Vinay B. Chikarmane, Brennan L. Peterson
Life of this patent
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Abstract
A method for forming a slot contact structure for n-type transistor performance enhancement. A slot contact opening is formed to expose a contact region, and a barrier plug is disposed within a portion of the slot contact opening in order to induce a tensile stress on an adjacent channel region. The remainder of the slot contact opening is filled with a lower resistivity contact metal. Barrier plug deposition temperature can be varied in order to tune the tensile stress on the adjacent channel region.
Claims21
An n-type semiconductor device comprising:
- an n-type transistor including a gate stack and a contact region, the gate stack defining a channel region thereunder;
- and
- a slot contact in contact with a portion of the contact region below the gate stack, the slot contact including an intrinsically stressed barrier plug and a contact metal;
- wherein the barrier plug induces a tensile stress on the channel region.
A method of forming an n-type semiconductor device comprising:
- forming an n-type transistor including a gate stack and a contact region, the gate stack defining a channel region thereunder;
- disposing a dielectric layer over the transistor;
- forming an opening in the dielectric layer to expose the contact region, the opening extending below the gate stack;
- disposing a barrier plug within a portion of the opening, the barrier plug inducing a tensile stress in the transistor channel region;
- and
- filling the remaining of the opening with a contact metal.
A method of forming an integrated semiconductor device comprising:
- forming an NMOS transistor including a first gate stack and a first contact region, the first gate stack defining a first channel region thereunder;
- forming a PMOS transistor including a second gate stack and a second contact region, the second gate stack defining a second channel region thereunder;
- disposing a dielectric layer over the NMOS and PMOS transistors;
- forming a first opening in the dielectric layer to expose the first contact region of the NMOS transistor, the opening extending below the first gate stack;
- forming a second opening in the dielectric layer to expose the second contact region the PMOS transistor, wherein the second opening does not extend below the second gate stack;
- disposing a barrier plug within a portion of the first and second openings, the barrier plug inducing a tensile stress on the first channel region;
- and
- filling the remaining of the first and second openings with a contact metal.
Dependencies are inferred from the claim text.