Dual stress sti

A semiconductor device, comprising:

• a substrate comprising a first transistor region and a second transistor region different than said first transistor region;
• and
• shallow trench isolation (STI) regions in said substrate adjacent sides of and positioned between said first transistor region and said second transistor region,
• wherein said STI regions each comprise a compressive region, a compressive liner, a tensile region, and a tensile liner.

A method, comprising:

• depositing an oxide layer and a nitride layer on a substrate;
• patterning said oxide layer, said nitride layer, and said substrate to form a first transistor region and a second transistor region within said substrate;
• a compressive layer above said first transistor region;
• depositing a tensile layer above said second transistor region;
• polishing said compressive layer and said tensile layer so as to form shallow trench isolation (STI) regions each comprising a compressive region and a tensile region adjacent sides of and positioned between said first transistor region and said second transistor region.

A method, comprising:

• depositing an oxide layer and a nitride layer on a substrate;
• patterning said oxide layer, said nitride layer, and said substrate to form a first transistor region and a second transistor region within said substrate;
• depositing a first compressive layer above said first transistor region, a second compressive layer above said first compressive layer, and a first tensile layer above said second transistor region;
• depositing a second tensile layer above said first tensile layer;
• polishing said second compressive layer, said second tensile layer, said first compressive layer, and said first tensile layer so as to form shallow trench isolation (STI) regions each comprising a compressive region, a compressive liner, a tensile region, and a tensile liner adjacent sides of and positioned between said first transistor region and said second transistor region.