Inter-Diffusion Barrier Structures for Dopants in Gate Electrodes, and Method for Manufacturing
AssigneeToshiba America Electronic Components, Inc.
InventorKatsura Miyashita
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AssigneeToshiba America Electronic Components, Inc.
InventorKatsura Miyashita
Estimating the term…
Structures for reducing or even preventing the diffusion from an NFET side of a gate to a PFET side of the gate in a semiconductor device are disclosed, as well as manufacturing methods thereof. A diffusion barrier is formed in the shared gate at the N/P boundary between the NFET and the PFET. The diffusion barrier is doped with one or more types of ions, such as, but not limited to, oxygen, nitrogen, fluorine, silicon, germanium, or xenon ions. By using a diffusion barrier as disclosed herein, the diffusion of ions through a common gate from the NFET side to the PFET side in a CMOS technology semiconductor device node may be significantly reduced or even prevented altogether. This may further result in relatively higher performance of the NFET/PFET pair.
A semiconductor device, comprising:
A semiconductor device, comprising:
A method for manufacturing a semiconductor device, comprising:
Dependencies are inferred from the claim text.