Stressed barrier plug slot contact structure for transistor performance enhancement

A method of forming a semiconductor device comprising:

• forming a transistor including a gate stack and a contact region, the gate stack defining a channel region thereunder;
• disposing a dielectric layer over the transistor;
• forming an opening in the dielectric layer to expose the contact region, the opening extending below the gate stack;
• disposing a barrier plug within a portion of the opening, the barrier plug inducing a stress in the transistor channel region;
• and
• filling the remaining of the opening with a contact metal.

A semiconductor structure comprising:

• a first transistor including a first gate stack and a first contact region, the first gate stack defining a first channel region thereunder;
• a second transistor including a second gate stack and a second contact region, the second gate stack defining a second channel region thereunder;
• a dielectric layer disposed over the first and second transistors;
• a contact opening formed in the dielectric layer, the opening exposing the first and second contact regions, the opening extending across an isolation region between the first transistor and second transistor;
• a barrier plug material disposed within a portion of the contact opening, wherein the barrier plug material induces a stress in the first and second channel regions;
• and
• a contact metal disposed on the barrier plug material.

A semiconductor structure comprising:

• a transistor including a gate stack and a contact region, the gate stack defining a channel region thereunder;
• and
• a slot contact in contact with a portion of the contact region below the gate stack, the slot contact being at least twice as long as it is wide;
• wherein the slot contact induces a stress on the channel region.