Stress liner surrounded facetless embedded stressor mosfet

A semiconductor structure comprising:

• a semiconductor substrate including at least one metal oxide semiconductor field effect transistor (MOSFET) located on a surface of said semiconductor substrate;
• an embedded stressor material located at a footprint of each of said FETs in a recessed area of said semiconductor structure;
• at least one trench isolation region located in said semiconductor substrate abutting said embedded stressor material, wherein said at least one trench isolation region is lined wig a stress liner thereby preventing embedded stressor facet growth at the boundary between the at least one trench isolation region and the embedded stressor material;
• and
• a nitride spacer that sticks out from upper sidewalls of said recessed area that contains said embedded stressor material as well as upper sidewalls of trenches used in defining the at least trench isolation region.