Dielectric extension to mitigate short channel effects
AssigneesSpansion LLC, Advanced Micro Devices, Inc.
InventorsVidyut Gopal, Shankar Sinha, Jean Yee-Mei Yang, Phillip L. Jones
Life of this patent
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Abstract
In patterning a transistor, some of a layer of gate dielectric material is allowed to remain over a semiconductor substrate upon which the transistor is formed. This remaining dielectric material retards the implantation of dopants into the underlying substrate, effectively lengthening a channel region of the transistor. This mitigates unwanted short channel effects, such as leakage currents, for example, and thus mitigates yield loss by establishing a transistor that performs in a more predictable or otherwise desirable manner.
Claims20
A method of implementing dielectric extensions in transistor fabrication, comprising:
- patterning a layer of gate electrode material such that passivants accumulate on sidewalls of the patterned layer of gate electrode material;
- patterning a layer of gate dielectric material that underlies the patterned layer of gate electrode material, where the passivants inhibit patterning portions of the layer of gate dielectric material that underlie the passivants;
- removing the passivants to reveal dielectric extensions that extend out into apertures formed by the patterning of the layer of gate electrode material and the layer of gate dielectric material;
- and
- implanting dopants into a semiconductor substrate that underlies the patterned layer of gate dielectric material to establish source/drain regions in the substrate, where the dielectric extensions substantially block the dopants such that a channel regions defined between the source/drain regions has a length that is greater than a channel length if the dielectric extensions were not present to block the dopants.
A transistor, comprising:
- a gate stack comprising:
- a gate dielectric formed on a semiconductor substrate;
- a gate electrode formed over the gate dielectric, the gate electrode having a width that is less than a width of the gate dielectric such that a first dielectric extension protrudes from a first side of the gate stack and a second dielectric extension protrudes from a second side of the gate stack.
- a source region formed in the substrate that is substantially aligned with the first dielectric extension;
- a drain region formed in the substrate that is substantially aligned with the second dielectric extension;
- and
- a channel region defined in the substrate between the source and drain regions that has a length that is greater than a length of a channel region established in the substrate in the absence of the dielectric extensions.
An electronic device, comprising:
- a user input configured to allow a user to input data;
- a user output configured to output data to a user;
- a central processing unit (CPU) operatively coupled to the user input and the user output and configured to receive and process the user input to output the user output;
- and
- a memory operatively coupled to the CPU and configured to receive data from and send data to the CPU, the memory comprising at least one transistor comprising
- a gate stack comprising:
- a gate dielectric formed on a semiconductor substrate;
- a gate electrode formed over the gate dielectric, the gate electrode having a width that is less than a width of the gate dielectric such that a first dielectric extension protrudes from a first side of the gate stack and a second dielectric extension protrudes from a second side of the gate stack.
- a source region formed in the substrate that is substantially aligned with the first dielectric extension;
- a drain region formed in the substrate that is substantially aligned with the second dielectric extension;
- and
- a channel region defined in the substrate between the source and drain regions that has a length that is greater than a length of a channel region established in the substrate in the absence of the dielectric extensions.
Dependencies are inferred from the claim text.