LDPMOS structure with enhanced breakdown voltage

A semiconductor structure comprising:

• a substrate;
• a first well region of a first conductivity type overlying the substrate;
• a second well region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first well region;
• a third well region of the second conductivity type adjacent the first well region, wherein the second and the third well regions are spaced apart from each other by a spacing;
• a deep well region of the second conductivity type underlying the first, the second and the third well regions, wherein a portion of the deep well region directly underlying the spacing has a first impurity concentration, and wherein portions of the deep well region directly underlying the first and the second well regions have a second impurity concentration, and wherein the first impurity concentration is less than the second impurity concentration;
• an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region;
• a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region;
• and
• a gate electrode on the gate dielectric.

A semiconductor structure comprising:

• a semiconductor substrate;
• a first low-voltage p-well (LVPW) region overlying the substrate;
• a first low-voltage n-well (LVNW) region overlying the substrate and laterally adjoining the first LVPW region;
• a second LVNW region overlying the substrate and encircling the first LVNW region and the first LVPW region, wherein the second LVNW region is spaced apart from the first LVNW region and the first LVPW region;
• a first deep n-well (DNW) region underlying at least portions of first LVNW region and the first LVPW region;
• a second DNW region underlying the second LVNW region and laterally spaced apart from the first DNW region;
• an insulation region in the first LVPW region, the insulation region having a top surface substantially level with a top surface of the first LVPW region;
• a gate dielectric extending from over the insulation region to over the first LVNW region;
• a gate electrode on the gate dielectric;
• a drain region in the first LVPW region and adjacent the insulation region;
• and
• a source region in the first LVNW region and adjacent the gate dielectric.

A method for forming a semiconductor structure, the method comprising:

• providing a substrate;
• forming a first well region of a first conductivity type overlying the substrate;
• forming a second well region of a second conductivity type overlying the substrate and laterally adjoining the first well region, wherein the second conductivity type is opposite the first conductivity type;
• forming a third well region of the second conductivity type adjacent the first well region, wherein the second and the third well regions are spaced apart from each other;
• forming a first deep well region of the second conductivity type underlying at least portions of the first and the second well regions;
• forming a second deep well region of the second conductivity type underlying the third well region, wherein the first and the second deep well regions are spaced apart by a spacing;
• forming an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region;
• forming a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region;
• and
• forming a gate electrode on the gate dielectric.