Transistors with laterally extended active regions and methods of fabricating same
AssigneeSamsung Electronics Co., Ltd.
InventorsSung-Sam LEE, Min-Hee CHO
Life of this patent
Estimating the term…
Abstract
A transistor and method of fabricating the transistor are disclosed. The transistor is disposed in an active region of a substrate defined by an isolation region and includes a gate electrode and associated source/drain regions. The isolation region includes an upper isolation region and an lower isolation region, wherein the upper isolation region is formed with sidewalls having, at least in part, a positive profile.
Claims25
A transistor disposed on a substrate in relation to an isolation region, the transistor comprising:
- a gate electrode and associated source/drain regions,
- wherein the isolation region is disposed in the substrate to define an active region, the isolation region including an upper isolation region defining an upper active region and an lower isolation region defining a lower active region, wherein the upper isolation region is formed with sidewalls having, at least in part, a positive profile;
- the gate electrode extends through the upper active region into the lower active region;
- and,
- the source/drain regions are disposed in the active region on respective sides of the gate electrode.
A semiconductor memory device comprising:
- an array of memory cells and at least one peripheral circuit associated with the array, wherein each memory cell in the array comprises at least one lateral extended transistor, the lateral extended transistor comprising a gate electrode and associated source/drain regions,
- wherein each memory cell in the array is formed in an active region of a substrate defined by an isolation region, the isolation region including an upper isolation region defining an upper active region and an lower isolation region defining a lower active region, wherein the upper active region has, at least in part, a concave sidewall;
- the gate electrode extends through the upper active region into the lower active region;
- and,
- the source/drain regions are disposed in the active region on respective sides of the gate electrode.
A method of fabricating a transistor, the method comprising:
- forming an isolation trench in a substrate to define an active region, the isolation trench comprising an upper isolation trench having sidewalls including, at least in part, a negative profile and a lower isolation trench formed through a bottom surface of the upper isolation trench, wherein the lower isolation trench has a width less than or equal to a minimal width of the upper isolation trench, and wherein the upper isolation trench defines an upper active region in the active region and the lower isolation trench defines a lower active region in the active region having a width greater than or equal to the width of the upper active region;
- filling the isolation trench with an insulating material;
- forming a gate electrode extending through the upper active region into the lower active region;
- and
- forming source/drain regions in the active region on respective sides of the gate electrode.
A method of forming a recessed channel array transistor (RCAT) in an active region of a semiconductor substrate, the method comprising:
- forming a recessed channel region in the substrate to separate source/drain regions of the RCAT and define a channel between the source/drain regions;
- forming a gate electrode structure in the recessed channel region contacting the source/drain regions;
- separating the active region from an adjacent active region by forming an isolation trench in the substrate and filling the isolation trench with an insulating material, wherein formation of the isolation trench reduces the contact area between the gate electrode structure and the source/drain regions, and reduces the size of a depletion region associated with the channel without reducing the width of the channel.
Dependencies are inferred from the claim text.