Semiconductor device having recess channel structure and method for manufacturing the same
AssigneeHynix Semiconductor Inc.
InventorKang Sik CHOI
Life of this patent
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Abstract
A semiconductor device having a recess channel structure includes a semiconductor substrate having a recess formed in a gate forming area in an active area; an insulation layer formed in the semiconductor substrate so as to define the active area and formed so as to apply a tensile stress in a channel width direction; a stressor formed in a surface of the insulation layer and formed so as to apply a compressive stress in a channel height direction; a gate formed over the recess in the active area; and source/drain areas formed in a surface of the active area at both side of the gate.
Claims19
A semiconductor device comprising:
- a semiconductor substrate having a recess in an active region;
- an isolation structure formed in the semiconductor substrate and defining the active region, the isolation structure applying a stress of a first type in a channel width direction;
- a stressor formed at least partly within the isolation structure and configured to apply a stress of a second type in a channel height direction;
- a gate formed at least partly within the recess in the active region;
- and
- first and second doped regions formed respectively on first and second sides of the gate.
A method for manufacturing a semiconductor device, comprising:
- forming an isolation structure in a semiconductor substrate to define an active region, the isolation structure configured to apply a stress of a first type in a channel width direction;
- forming a stressor at least partly within the isolation structure, the stressor being configured to apply a stress of a second type in a channel height direction;
- forming first and second doped regions in the active region;
- forming a recess in the active area;
- and
- forming a gate between the first and second doped regions, the gate being at least partly within the recess.
A semiconductor device comprising:
- first and second doped regions defined in an active region of a substrate;
- a gate defined between the first and second doped regions and configured to control a current flow between the first and second doped regions;
- an isolation structure formed in the semiconductor substrate and defining the active region, the isolation structure applying a stress of a first type in a channel width direction;
- and
- a stressor formed at least partly within the isolation structure and configured to apply a stress of a second type in a channel height direction.
Dependencies are inferred from the claim text.