Convex shaped thin-film transistor device
AssigneeSpansion LLC
InventorsYukio Hayakawa, Hiroyuki Nansei
Life of this patent
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Abstract
The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density, and a method of manufacturing such a semiconductor device. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines on the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed.
Claims20
A semiconductor device comprising:
- first bit lines that are provided on a substrate;
- an insulating layer that is provided between the first bit lines on the substrate, wherein the upper face of the insulating layer is higher than the upper faces of the first bit lines;
- channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines;
- and
- charge storage layers that are provided on opposite side faces of the channel layers from the side faces on which the insulating layers are formed.
A method of manufacturing a semiconductor device, comprising:
- forming first bit lines on a substrate;
- forming an insulating layer between the first bit lines, wherein the upper face of the insulating layer is higher than the upper faces of the first bit lines;
- forming channel layers on both side faces of the insulating layer;
- and
- forming charge storage layers on opposite side faces of the channel layers from the side faces on which the insulating film is provided.
A method of manufacturing a semiconductor device, comprising:
- forming insulating layers by performing etching on predetermined regions of a substrate;
- forming a layer to be channel layers on the substrate, the layer covering the insulating layers;
- forming first bit lines and channel layers from the layer to be channel layers by implanting ions into portions of the layer to be channel layers, the portions being located between the insulating layers and above the insulating layers;
- and
- forming charge storage layers on opposite side faces of the channel layers from the side faces on which the insulating layers are formed.
A system, comprising:
- a processor;
- a cache;
- a user input component;
- and
- a flash memory comprising:
- first bit lines that are provided on a substrate;
- an insulating layer that is provided between the first bit lines on the substrate, wherein the upper face of the insulating layer is higher than the upper faces of the first bit lines;
- channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines;
- and
- charge storage layers that are provided on opposite side faces of the channel layers from the side faces on which the insulating layers are formed.
Dependencies are inferred from the claim text.