Local interconnect having increased misalignment tolerance

A semiconductor device, comprising:

• a substrate having a source region formed in an active region;
• a pair of source select transistors formed above the substrate on opposite sides of the source region;
• a first inter-layer dielectric formed above the substrate in between the pair of source select transistors;
• and
• a local interconnect comprising a metal formed adjacent the first inter-layer dielectric,
• wherein the local interconnect has a width narrower than a distance between the pair of source select transistors.

A method of fabricating a semiconductor device having a pair of select transistors formed over a substrate, comprising:

• forming a source region between the pair of select transistors, the source region have a silicide region formed in an upper surface thereof;
• forming a liner oxide layer over the pair of select transistors and the source region;
• forming spacers adjacent the interior sidewalls of the pair of select transistors over the liner oxide layer;
• depositing a inter-layer dielectric between the spacers;
• etching the inter-layer dielectric and the liner oxide layer to form an interconnect area have a width less than a distance between the pair of select transistors;
• and
• forming a metal contact within the interconnect area.