Semiconductor device capacitor fabrication method
AssigneeDongbu HiTek Co., Ltd.
InventorJung-Ho Ahn
Life of this patent
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Abstract
A semiconductor device capacitor fabrication method that is capable of enabling the simultaneous use of an oxide capacitor and a PIP capacitor of a semiconductor device depending upon whether metal line terminals are used. The semiconductor device capacitor fabrication method can include forming an active region and a first gate electrode over a semiconductor substrate, partially depositing a silicon nitride layer, over which a capacitor will be formed, over the first gate electrode, forming a second gate electrode over the silicon nitride, sequentially forming a first insulation layer and a second insulation layer over the resultant structure and forming line terminals extending through the first insulating layer and the second insulating layer for a transistor and a capacitor.
Claims20
A method comprising:
- forming an active region, a P-well and at least one shallow trench isolation region in a semiconductor substrate;
- forming a first gate electrode over the semiconductor substrate;
- forming a first photoresist pattern over the first gate electrode;
- depositing a silicon nitride layer partially over the photoresist pattern;
- forming a second gate electrode over the silicon nitride layer;
- sequentially forming a first insulation layer and a second insulation layer over the semiconductor substrate;
- forming a second photoresist pattern over the second insulation layer;
- forming a plurality of holes extending through the first insulating layer and the second insulating layer;
- and then
- completing the formation of a semiconductor device by forming line terminals for a transistor and a capacitor by filling the holes with a metal material.
A method comprising:
- providing a semiconductor substrate having an active region and at least one shallow trench isolation region;
- forming a first gate electrode over the semiconductor substrate;
- forming a nitride layer partially over the first gate electrode;
- forming a second gate electrode over the nitride layer;
- forming a first insulation layer over the semiconductor substrate including the first gate electrode and the second gate electrode;
- forming a second insulation layer over the semiconductor substrate including the first insulating layer;
- and then
- forming a plurality of line terminals extending through the first insulating layer and the second insulating layer and in contact with the active region, the semiconductor substrate, the first gate electrode and the second gate electrode.
The method of clam 11, wherein forming plurality of line terminals comprises:
- forming a plurality of holes extending through the first insulation layer and the second insulation layer to expose the uppermost surface of the semiconductor substrate, the active region, the first gate electrode, and the second gate electrode;
- and then
- filling the plurality of holes with a metal material.
An apparatus comprising:
- a semiconductor substrate having an active region, a P-well and a pair of shallow trench isolation regions;
- a first gate electrode formed over the semiconductor substrate;
- a nitride layer formed partially over the first gate electrode;
- a second gate electrode formed over the nitride layer;
- a first insulation layer formed over the semiconductor substrate including the first gate electrode and the second gate electrode;
- a second insulation layer formed over the semiconductor substrate including the first insulating layer;
- and
- a plurality of line terminals extending through the first insulating layer and the second insulating layer and in contact with the active region, the P-well, the first gate electrode and the second gate electrode.
Dependencies are inferred from the claim text.