Cmos image sensor and fabricating method thereof

A CMOS image sensor comprising:

• an epitaxial layer formed on a semiconductor substrate, the epitaxial layer comprising a pixel area including a plurality of photodiodes and a logic area including a plurality of devices capable of performing signal processing;
• an insulating layer formed on the epitaxial layer, the insulating layer including a plurality of wells, a plurality of STI (shallow trench isolation) layers formed on a plurality of the wells, and a plurality of source and drain regions;
• a gate pattern formed on the insulating layer in both the pixel area and the logic area, the gate pattern having a spacer on both sides;
• a salicide blocking layer formed on the insulating layer including and gate pattern in the pixel area;
• a plurality of silicide layers formed on either side of the gate pattern in the logic area;
• a PMD liner nitride layer formed on the salicide blocking layer in the pixel area and the insulating layer and gate pattern in the logic area;
• a PSG (phosphosilicate glass) layer formed on the PMD liner nitride layer;
• and
• a plurality of contacts which connect the surface of the PSG layer to a plurality of source and drain regions next to the STI layers.

A method of fabricating a CMOS mage sensor, comprising:

• forming an epitaxial layer on a semiconductor substrate, the epitaxial layer comprising a pixel area including a plurality of photodiodes and a logic area including a plurality of devices capable of performing signal processing;
• forming an STI (shallow trench isolation) layer in an insulating layer formed on the epitaxial layer;
• forming a plurality of wells and a gate pattern having a spacer on the insulating layer having the STI layer;
• forming a plurality of source and drain regions in the insulating layer using an ion implantation process;
• forming a salicide blocking layer on the insulating layer and gate pattern in the pixel area by depositing an oxide layer and a nitride layer on the insulating layer and gate pattern in the pixel area in order to prevent salicidation in the pixel area;
• forming a photoresist pattern on the salicide blocking layer;
• removing the salicide blocking layer in the logic area using the photoresist pattern as a mask in an etching process;
• depositing a high melting point metal on the semiconductor substrate over photoresist pattern;
• removing the photoresist pattern by performing an ashing process;
• and
• performing a rapid annealing process to form a silicide layer;
• sequentially forming a PMD liner nitride layer and a PSG (phosphosilicate glass) layer on the salicide blocking layer in the pixel area and the insulating layer and the gate pattern in the logic area;
• and
• forming a plurality of contacts from a surface of the PSG layer to the plurality of source and drain regions.