Method of forming a selective spacer in a semiconductor device

Abstract

A selective spacer for semiconductor and MEMS devices and method of manufacturing the same. In an embodiment, a selective spacer is formed adjacent to a first non-planar body having a greater sidewall height than a second non-planar semiconductor body in a self-aligned manner requiring no patterned etch operations. In a particular embodiment, a margin layer of a particular thickness is utilized to augment an existing structure and provide sufficient margin to protect a sidewall with a spacer that is first anisotropically defined and then isotropically defined. In another embodiment, the selective spacer formation prevents etch damage by terminating the anisotropic etch before a semiconductor surface is exposed.

Dependencies are inferred from the claim text.