Stack SiGe for short channel improvement

A metal-oxide-semiconductor (MOS) device comprising:

• a semiconductor substrate;
• a gate stack on the semiconductor substrate;
• and
• a stressor having at least a portion in the semiconductor substrate and adjacent the gate stack, wherein the stressor comprises:
• a first stressor region having a first impurity concentration;
• a second stressor region having a second impurity concentration on the first stressor region;
• and
• a third stressor region having a third impurity concentration on the second stressor region, wherein the second impurity concentration is substantially lower than the first and the third impurity concentrations.

A metal-oxide-semiconductor (MOS) device comprising:

• a semiconductor substrate;
• a gate stack on the semiconductor substrate;
• a lightly-doped source/drain (LDD) region;
• and
• a SiGe stressor having at least a portion in the semiconductor substrate and adjacent the gate stack, wherein the SiGe stressor comprises:
• a first SiGe region doped with a p-type impurity having a first impurity concentration;
• a second SiGe region doped with a p-type impurity having a second impurity concentration;
• and
• a third SiGe region doped with a p-type impurity having a third impurity concentration, wherein the second impurity concentration is substantially lower than the first and the third impurity concentration.