Memory device
AssigneeInfineon Technologies AG
InventorShoaib Hasan Zaidi
Life of this patent
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Abstract
A phase change memory cell is disclosed. The phase change memory cell includes a first thin film spacer and a second thin film spacer. The first thin film spacer defines a sub-lithographic dimension and is electrically coupled to a first electrode. The second thin film spacer defines a sub-lithographic dimension and is electrically coupled between a second electrode and the first thin film spacer. In this regard, the phase change memory cell is formed at a boundary where the first thin film spacer electrically contacts the second thin film spacer.
Claims24
An integrated circuit having a resistivity changing cell comprising:
- a first thin film spacer defining a sub-lithographic dimension and electrically coupled to a first electrode;
- and
- a second thin film spacer defining a sub-lithographic dimension,
- wherein the resistivity changing cell is formed at a boundary where the first thin film spacer electrically contacts the second thin film spacer.
A method of forming a phase change memory cell comprising:
- forming a first thin film spacer defining a first sidewall and electrically coupled to a first electrode;
- forming a second thin film spacer defining a second sidewall, the second thin film spacer electrically coupled to a second electrode and formed non-parallel to the first thin film spacer, the second thin film spacer tilted relative to the first thin film spacer at an angle between 70-110 degrees;
- and
- means for electrically contacting the first thin film spacer to the second thin film spacer across a sub-lithographic contact area of between approximately 18-22 nanometers square.
A method of forming an array of phase change memory cells on a chip comprising:
- forming a plurality of columns of first spacers onto a substrate of the chip;
- forming a plurality of rows of second spacers to electrically contact the plurality of columns of first spacers, at least one of the columns of first spacers and rows of second spacers including phase change material;
- and
- etching the plurality of columns of first spacers and the plurality of rows of second spacers to form a plurality of phase change memory cells.
A method of forming a phase change memory cell on a chip comprising:
- block exposure forming a first thin film spacer defining sub-lithographic dimensions onto a first electrode;
- block exposure forming a second thin film spacer defining sub-lithographic dimensions, the second thin film spacer in electrical contact with the first thin film spacer and a second electrode;
- and
- etching the first and second thin film spacers to isolate a phase change memory cell at an intersection of the first thin film spacer with the second thin film spacer.
An electronic system comprising:
- an electronic device;
- and
- a memory device electrically coupled to the electronic device, the memory device comprising at least one phase change memory cell defining:
- a first thin film spacer defining a sub-lithographic dimension and electrically coupled to a first electrode,
- a second thin film spacer defining a sub-lithographic dimension and electrically coupled between a second electrode and the first thin film spacer;
- wherein the at least one phase change memory cell is formed at a boundary where the first thin film spacer electrically contacts the second thin film spacer.
Dependencies are inferred from the claim text.