Optical semiconductor device having active layer of p-type quantum dot structure and its manufacture method

A method for manufacturing an optical semiconductor device comprising steps of:

• (a) forming an active layer having a p-type quantum dot structure over a lower cladding layer made of semiconductor material of a first conductivity type;
• (b) forming an upper cladding layer made of semiconductor material of a second conductivity type opposite to the first conductivity type over the active layer;
• (c) covering an upper surface of the upper cladding layer in an area extending in one direction, with a mask pattern;
• (d) by using the mask pattern as an etching mask, etching the upper cladding layer partway in a thickness direction thereof;
• (e) by using the mask pattern as a mask, implanting or diffusing impurities into the upper cladding layer to make the upper cladding layer have the first conductivity type or high resistance to form a capacitance reducing region;
• and
• (f) removing the mask pattern,
• wherein the capacitance reducing region formed in the step (e) reaches at least an upper surface of the active layer if the lower cladding layer is a p-type, and reaches at least an upper surface of the lower cladding layer if the lower cladding layer is an n-type.

A method for manufacturing an optical semiconductor device comprising steps of:

• (a) forming an active layer having a p-type quantum dot structure over a lower cladding layer made of semiconductor material of a first conductivity type;
• (b) forming an upper cladding layer made of semiconductor material of a second conductivity type opposite to the first conductivity type over the active layer;
• (c) covering an upper surface of the upper cladding layer in an area extending in one direction, with a first mask pattern;
• (d) by using the first mask pattern as a mask, implanting or diffusing impurities into the upper cladding layer to make the upper cladding layer have the first conductivity type or high resistance to form a capacitance reducing region;
• (e) removing the first mask pattern;
• (f) covering an inner area spaced by a distance from each of both side edges of the area covered with the first mask pattern, with a second mask pattern;
• and
• (g) by using the second mask pattern as an etching mask, etching the upper cladding layer partway in a thickness direction thereof,
• wherein:
• the capacitance reducing region formed in the step (d) reaches at least an upper surface of the active layer if the lower cladding layer is a p-type, and reaches at least an upper surface of the lower cladding layer if the lower cladding layer is an n-type;
• and
• a plan shape of the second mask pattern is set in such a manner that after etching in the step (g), the capacitance reducing region is spaced apart in an in-plane direction by a distance from the second mask pattern.