# US 2008/0141019 A1 · Data Processing Apparatus Including Reconfigurable Logic Circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2008/0141019 A1 - Document ID: US20080141019A1 - Status: Published application - Kind: A1 - Application number: 11/718,195 - Filed: 2005-10-28 - Published: 2008-06-12 - Earliest claimed: 2004-10-28 - Assignees: Ipflex Inc. - Inventors: Hiroki Honda - Web page: https://patentgrep.com/patent/US20080141019A1 ## CPC - G06F 30/347: Physical level, e.g. placement or routing - G06F 15/7867: {with reconfigurable architecture} - G06F 30/33: Design verification, e.g. functional simulation or model checking - G06F 30/3308: using simulation - G06F 30/331: with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation - G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] - G06F 11/261: {by simulating additional hardware, e.g. fault simulation} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract There is provided a data processing apparatus (1) including a logic circuit (10) that is reconfigurable in each cycle and a library (2) that stores hardware control information (20). The hardware control information (20) includes a plurality of pieces of cycle-based mapping information (21) for individually mapping a plurality of cycle-based circuits, which each realize a function in each cycle for executing an application, onto the logic circuit (10) and configuration selection information (22) for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application. The data processing apparatus (1) includes a control unit (11) that reconfigures at least part of the logic region (10) using at least one of the plurality of pieces of cycle-based mapping information (21) according to a request in each cycle based on the configuration selection information (22). ## Claims ### Claim 1 A data processing apparatus comprising: a logic circuit that is reconfigurable in each cycle; and a library in which hardware control information is stored, wherein the hardware control information includes: a plurality of pieces of cycle-based mapping information for mapping a plurality of cycle-based circuits onto the logic circuit individually, each of the plurality of cycle-based circuits realizing a function in each cycle for executing an application; and configuration selection information for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application, and the data processing apparatus further comprises: a control unit that reconfigures, according to a request in each cycle based on the configuration selection information, at least part of the logic circuit using at least one of the plurality of pieces of cycle-based mapping information. ### Claim 2 (depends on 1) The data processing apparatus according to claim 1, wherein the plurality of pieces of cycle-based mapping information include a piece of composite cycle-based mapping information produced by merging pieces of cycle-based mapping information that are capable of being merged without obstructing functions in each cycle. ### Claim 3 (depends on 1) The data processing apparatus according to claim 1, wherein each of the plurality of pieces of cycle-based mapping information includes information for mapping a control unit for each cycle onto the logic circuit, and the control unit for each cycle is reconfigured in the logic circuit. ### Claim 4 A data processing apparatus comprising: a logic circuit that is reconfigurable in each cycle; and a library in which hardware control information is stored, wherein the hardware control information includes: a plurality of pieces of cycle-based mapping information for mapping a plurality of cycle-based circuit onto the logic circuit individually, each of the plurality of cycle-based circuits realizing a function in each cycle for executing an application; and configuration selection information for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application, and at least part of the logic circuit is reconfigured using at least one of the plurality of pieces of cycle-based mapping information according to a request in each cycle based on the configuration selection information. ### Claim 5 (depends on 4) The data processing apparatus according to claim 4, wherein each of the plurality of pieces of cycle-based mapping information includes information for mapping a control unit for each cycle onto the logic circuit, and at least part of the logic circuit is reconfigured according to a request of the control unit in each cycle reconfigured in the logic circuit. ### Claim 6 A method of controlling a data processing apparatus, which includes a logic circuit that is reconfigurable in each cycle, comprising a step of reconfiguring at least part of the logic circuit based on hardware control information, wherein the hardware control information includes: a plurality of pieces of cycle-based mapping information for mapping a plurality of cycle-based circuits onto the logic circuit individually, each of the plurality of cycle-based circuits realizing a function in each cycle for executing an application; and configuration selection information for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application, and the step of reconfiguring includes selecting at least one of the plurality of pieces of cycle-based mapping information according to a request in each cycle based on the configuration selection information and reconfiguring at least part of the logic circuit using selected piece of cycle-based mapping information. ### Claim 7 (depends on 6) The data processing apparatus according to claim 6, wherein each of the plurality of pieces of cycle-based mapping information includes information for mapping a control unit for each cycle onto the logic circuit, and the step of reconfiguring includes reconfiguring at least part of the logic circuit according to a request of the control unit for each cycle that has been reconfigured in the logic circuit. ### Claim 8 A generation system for generating hardware control information for controlling a reconfigurable logic circuit, the generation system comprising: a functional unit for generating circuit information of a plurality of cycle-based circuits that each realize a function in each cycle for executing an application; and a functional unit for generating the hardware control information, the hardware control information including a plurality of pieces of cycle-based mapping information for mapping the plurality of cycle-based circuits onto the logic circuit individually and configuration selection information for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application. ### Claim 9 (depends on 8) The generation system according to claim 8, further comprising a functional unit for generating composite cycle-based mapping information by extracting, out of the plurality of pieces of cycle-based mapping information, pieces of cycle-based mapping information that are capable of being merged without obstructing functions in each cycle and merging the pieces of cycle-based mapping information extracted. ### Claim 10 (depends on 8) The generation system according to claim 8, wherein the functional unit for generating the hardware control information includes generating a piece of configuration selection information in each cycle and merging the piece of configuration selection information with a piece of cycle-based mapping information. ### Claim 11 (depends on 8) The generation system according to claim 8, wherein the functional unit for generating the circuit information includes generating information of the plurality of cycle-based circuits based on a control data flow graph for executing the application. ### Claim 12 (depends on 8) The generation system according to claim 8, wherein the functional unit for generating the circuit information includes resolving RTL for executing the application on a cycle basis and generating information of the plurality of cycle-based circuits. ### Claim 13 A method of generating hardware control information for controlling a reconfigurable logic circuit, the method comprising the steps of: generating circuit information of a plurality of cycle-based circuits that each realize a function in each cycle for executing an application; and generating the hardware control information, the hardware control information including a plurality of pieces of cycle-based mapping information for mapping the plurality of cycle-based circuits onto the logic circuit individually and configuration selection information for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application. ### Claim 14 (depends on 13) The method according to claim 13, further comprising a step of generating composite cycle-based mapping information that includes extracting, out of the plurality of pieces of cycle-based mapping information, pieces of cycle-based mapping information that are capable of being merged without obstructing functions in each cycle and merging the pieces of cycle-based mapping information extracted. ### Claim 15 (depends on 13) The method according to claim 13, wherein the step of generating the hardware control information includes generating a piece of configuration selection information in each cycle and merging the piece of configuration selection information with a piece of cycle-based mapping information. ### Claim 16 (depends on 13) The method according to claim 13, wherein the step of generating the circuit information includes generating information of the plurality of cycle-based circuits based on a control data flow graph for executing the application. ### Claim 17 (depends on 13) The method according to claim 13, wherein the step of generating the circuit information includes resolving RTL for executing the application on a cycle basis and generating information of the plurality of cycle-based circuits. ### Claim 18 A recording medium on which hardware control information for controlling a data processing apparatus including a reconfigurable logic circuit is recorded, the hardware control information comprising: a plurality of pieces of cycle-based mapping information for mapping a plurality of cycle-based circuits onto the logic circuit individually, each of the a plurality of cycle-based circuits realizing a function in each cycle for executing an application; and configuration selection information for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application. ### Claim 19 (depends on 18) The recording medium according to claim 18, wherein the plurality of pieces of cycle-based mapping information include a piece of composite cycle-based mapping information produced by merging pieces of cycle-based mapping information that are capable of being merged without obstructing function in each cycle. ### Claim 20 (depends on 18) The recording medium according to claim 18, wherein the configuration selection information includes a plurality of pieces of cycle-based configuration selection information and a piece of cycle-based configuration selection information is merged with a piece of cycle-based mapping information.