Hierarchical register file

A method comprising:

• in a first-level register file:
• allocating a plurality of mappable registers so as to store execution results of instructions executed by a plurality of execution clusters in a hierarchical microprocessor;
• and
• providing secondary register storage for each of the plurality of execution clusters;
• in a plurality of second-level register files operatively coupled with the first-level register file:
• storing instruction operands;
• and
• providing the instruction operands to respective execution units of the execution clusters for use in executing associated instructions;
• and
• in a plurality of third-level register files operatively coupled with the first-level register file and respective second-level register files:
• providing operands to execution units;
• and
• capturing immediate literal values.

A microprocessor comprising:

• a plurality of execution clusters;
• a plurality of first-level architectural elements for processing instructions in the microprocessor, the plurality of first-level architectural elements being configured to act as shared resources for the plurality of execution clusters, wherein the plurality of first-level architectural elements includes a first-level register file including a plurality of mappable registers, wherein the first-level register filed is configured to:
• allocate the plurality of mappable registers so as to store execution results of instructions executed by the plurality of execution clusters;
• and
• provide secondary register storage for each of the plurality of execution clusters;
• a plurality of second-level register files operatively coupled with the first-level register file, the plurality of second-level register files being configured to:
• store instruction operands;
• and
• provide the instruction operands to respective execution units of the execution clusters for use in executing associated instructions;
• and
• a plurality of third-level register files operatively coupled with the first-level register file and respective second-level register files, the third-level register files being configured to:
• provide operands to execution units;
• and
• capture immediate literal values.

A hierarchical register file included in a hierarchical microprocessor including a plurality of execution clusters, the hierarchical register file comprising:

• a first-level register file including a plurality of mappable registers, wherein the first-level register filed is configured to:
• allocate the plurality of mappable registers so as to store execution results of instructions executed by the plurality of execution clusters;
• and
• provide secondary register storage for each of the plurality of execution clusters;
• a plurality of second-level register files operatively coupled with the first-level register file, the plurality of second-level register files being configured to:
• store instruction operands;
• and
• provide the instruction operands to respective execution units of the execution clusters for use in executing associated instructions;
• a plurality of third-level register files operatively coupled with the first-level register file and respective second-level register files, the third-level register files being configured to:
• provide operands to execution units;
• and
• capture immediate literal values;
• and
• a plurality of bypass caches configured to provide immediate literal values directly to respective execution units of the plurality of execution clusters prior to, or contemporaneously with, writing the immediate literal values to one or more of the first-level, second-level and third level register files,
• wherein:
• the first-level register file is shared between the plurality of execution clusters;
• each of the plurality of second-level register files is included in a respective execution cluster;
• and
• each of the plurality of third-level register files is included in a respective execution cluster.

A method comprising:

• in a first-level register file:
• allocating a plurality of mappable registers so as to store execution results of instructions executed by a plurality of execution clusters in a hierarchical microprocessor;
• and
• providing secondary register storage for each of the plurality of execution clusters;
• in a plurality of second-level register files operatively coupled with the first-level register file:
• storing instruction operands;
• and
• providing the instruction operands to respective execution units of the execution clusters for use in executing associated instructions;
• in a plurality of third-level register files operatively coupled with the first-level register file and respective second-level register files:
• providing operands to execution units;
• and
• capturing immediate literal values;
• and
• in a plurality of bypass caches:
• providing immediate literal values directly to respective execution units of the plurality of execution clusters prior to, or contemporaneously with, writing the immediate literal values to one or more of the first-level file, a respective second-level register file and a respective third-level register file.