Hierarchical instruction scheduler

A method for processing instructions in a microprocessor, the method comprising:

• receiving instructions for execution at a first-level instruction scheduler;
• storing first operand status information for respective operands of the instructions;
• dispatching, based on the first operand status information, the instructions to respective execution clusters of the microprocessor, wherein each of the respective execution clusters includes a corresponding second-level instruction scheduler, the second-level instruction schedulers being operatively coupled with the first-level instruction scheduler;
• receiving, at the second-level instruction schedulers, the instructions from the first-level instruction scheduler;
• storing second operand status information for respective operands of the instructions;
• dispatching, based on the second operand status information, the instructions to respective execution units of the execution clusters;
• and
• executing one of more of the instructions.

A microprocessor comprising:

• a plurality of execution clusters;
• a plurality of first-level architectural elements for processing instructions in the microprocessor, the plurality of first-level architectural elements being configured to act as shared resources for the plurality of execution clusters, wherein the plurality of first-level architectural elements includes a first-level instruction scheduler configured to:
• receive instructions for execution;
• store first operand status information for respective operands of the instructions;
• and
• dispatch the instructions to respective execution clusters of the plurality of execution clusters based on the first operand status information;
• and
• a plurality of second-level instruction schedulers, each of the second level instruction schedulers being included in a respective execution cluster of the plurality of execution clusters, wherein each of the second-level instructions schedulers is configured to:
• receive the instructions for execution from the first-level instruction scheduler;
• store second operand status information for respective operands of the instructions received from the first-level instruction scheduler;
• and
• dispatch the instructions, for execution, to respective execution units of the execution clusters based on the respective second operand status information.

A hierarchical instruction scheduler included in a hierarchical microprocessor including a plurality of execution clusters, the hierarchical instruction scheduler comprising:

• a first-level instruction scheduler configured to:
• receive instructions for execution;
• store first operand status information for respective operands of the instructions;
• and
• dispatch the instructions to respective execution clusters based on the instructions' respective first operand status information;
• and
• a plurality of second-level instruction schedulers each operatively coupled with the first-level instruction scheduler, each second-level instruction scheduler being included in a respective execution cluster, the second-level instruction schedulers each being configured to:
• receive instructions for execution from the first-level instruction scheduler;
• store second operand status information for respective operands of the instructions received from the first-level instruction scheduler;
• and
• dispatch instructions, for execution, to respective execution units of the execution clusters based on the instructions' respective second operand status information, wherein the first-level instruction scheduler includes:
• a timing wheel circuit configured to schedule the instructions based on respective predictions as to when one or more of the respective operands of the instructions will be available, the timing wheel circuit including a circular instruction buffer;
• and
• a picker circuit configured to notify the first-level instruction scheduler when one or more operands of a respective instruction become available, the picker circuit including a comparison circuit configured to determine when the one or more operands become available.

A method for processing instructions in a microprocessor, the method comprising:

• receiving instructions for execution at a first-level instruction scheduler;
• storing first operand status information for respective operands of the instructions;
• dispatching, based on the first operand status information, the instructions to respective execution clusters of the microprocessor, wherein each of the respective execution clusters includes a corresponding second-level instruction scheduler, the second-level instruction schedulers being operatively coupled with the first-level instruction scheduler;
• receiving, at the second-level instruction schedulers, the instructions from the first-level instruction scheduler;
• storing second operand status information for respective operands of the instructions;
• dispatching, based on the second operand status information, the instructions to respective execution units of the execution clusters;
• executing one of more of the instructions;
• and
• at least one of:
• (i) assigning an execution thread to a single execution cluster;
• and
• dispatching instructions associated with the execution thread to the single execution cluster;
• (ii) dispatching the instructions from the first-level instruction scheduler in accordance with a load balancing policy;
• and
• (iii) assigning a spawned thread to an execution cluster different than an execution cluster executing an associated spawning thread.